mirror of
https://git.hardenedbsd.org/hardenedbsd/HardenedBSD.git
synced 2024-11-22 03:04:34 +01:00
d3916eace5
Add kernel code for 'H' — Hypervisor Extension[1] to support virtualization on RISC-V ISA. This comes with a separate userspace patch allowing us to boot unmodified freebsd/riscv guest. Other operating systems are untested. This also comes with a U-Boot port that is configured to run in bhyve guest environment — in RISC-V virtual supervisor mode. The vmm SBI code emulates RISC-V machine-mode for the guest, handling SBI calls partly in vmm kernel and partly in bhyve userspace. Developed in Spike simulator during short period of time, the support is considered experimental. The first real hardware with hypervisor spec included should have just reached the market, so this was tested in Spike and QEMU only. Note that this depends on Sstc extension presence in the hardware (both Spike and QEMU have it). Note that booting multiple guests at the same time is not tested and may require additional work. Some TODOs are indicated within the code, and some listed in the project's home page[2]. Many thanks to Jessica Clarke, Mitchell Horne and Mark Johnston for help with parts, test and review. 1. https://riscv.org/technical/specifications/ 2. https://wiki.freebsd.org/riscv/bhyve Sponsored by: UK Research and Innovation Differential Revision: https://reviews.freebsd.org/D45553
89 lines
3.0 KiB
C
89 lines
3.0 KiB
C
/*-
|
|
* Copyright (c) 1996-1997 John D. Polstra.
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
* SUCH DAMAGE.
|
|
*/
|
|
|
|
#ifndef _MACHINE_ELF_H_
|
|
#define _MACHINE_ELF_H_
|
|
|
|
/*
|
|
* ELF definitions for the RISC-V architecture.
|
|
*/
|
|
|
|
#include <sys/elf32.h> /* Definitions common to all 32 bit architectures. */
|
|
#include <sys/elf64.h> /* Definitions common to all 64 bit architectures. */
|
|
|
|
#define __ELF_WORD_SIZE 64 /* Used by <sys/elf_generic.h> */
|
|
#include <sys/elf_generic.h>
|
|
|
|
/*
|
|
* Auxiliary vector entries for passing information to the interpreter.
|
|
*/
|
|
|
|
typedef struct { /* Auxiliary vector entry on initial stack */
|
|
int a_type; /* Entry type. */
|
|
union {
|
|
int a_val; /* Integer value. */
|
|
} a_un;
|
|
} Elf32_Auxinfo;
|
|
|
|
typedef struct { /* Auxiliary vector entry on initial stack */
|
|
long a_type; /* Entry type. */
|
|
union {
|
|
long a_val; /* Integer value. */
|
|
void *a_ptr; /* Address. */
|
|
void (*a_fcn)(void); /* Function pointer (not used). */
|
|
} a_un;
|
|
} Elf64_Auxinfo;
|
|
|
|
__ElfType(Auxinfo);
|
|
|
|
#define ELF_ARCH EM_RISCV
|
|
|
|
#define ELF_MACHINE_OK(x) ((x) == (ELF_ARCH))
|
|
|
|
/* Define "machine" characteristics */
|
|
#define ELF_TARG_CLASS ELFCLASS64
|
|
#define ELF_TARG_DATA ELFDATA2LSB
|
|
#define ELF_TARG_MACH EM_RISCV
|
|
#define ELF_TARG_VER 1
|
|
|
|
/* TODO: set correct value */
|
|
#define ET_DYN_LOAD_ADDR 0x100000
|
|
|
|
/* Flags passed in AT_HWCAP */
|
|
#define HWCAP_ISA_BIT(c) (1 << ((c) - 'a'))
|
|
#define HWCAP_ISA_I HWCAP_ISA_BIT('i')
|
|
#define HWCAP_ISA_M HWCAP_ISA_BIT('m')
|
|
#define HWCAP_ISA_A HWCAP_ISA_BIT('a')
|
|
#define HWCAP_ISA_F HWCAP_ISA_BIT('f')
|
|
#define HWCAP_ISA_D HWCAP_ISA_BIT('d')
|
|
#define HWCAP_ISA_C HWCAP_ISA_BIT('c')
|
|
#define HWCAP_ISA_H HWCAP_ISA_BIT('h')
|
|
#define HWCAP_ISA_G \
|
|
(HWCAP_ISA_I | HWCAP_ISA_M | HWCAP_ISA_A | HWCAP_ISA_F | HWCAP_ISA_D)
|
|
#define HWCAP_ISA_B HWCAP_ISA_BIT('b')
|
|
|
|
#endif /* !_MACHINE_ELF_H_ */
|