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69 lines
2.4 KiB
C
69 lines
2.4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __QCOM_CLK_BRANCH2_H__
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#define __QCOM_CLK_BRANCH2_H__
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#include "qcom_clk_freqtbl.h"
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/* halt is 1 */
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#define QCOM_CLK_BRANCH2_BRANCH_HALT 0
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/* halt is inverted (ie, 0) */
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#define QCOM_CLK_BRANCH2_BRANCH_HALT_INVERTED 1
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/* Don't check the bit, just delay */
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#define QCOM_CLK_BRANCH2_BRANCH_HALT_DELAY 2
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/* Don't check the halt bit at all */
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#define QCOM_CLK_BRANCH2_BRANCH_HALT_SKIP 3
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/* Flags */
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#define QCOM_CLK_BRANCH2_FLAGS_CRITICAL 0x1
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#define QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT 0x2
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struct qcom_clk_branch2_def {
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struct clknode_init_def clkdef;
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uint32_t flags;
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uint32_t enable_offset; /* enable register*/
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uint32_t enable_shift; /* enable bit shift */
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uint32_t hwcg_reg; /* hw clock gate register */
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uint32_t hwcg_bit;
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uint32_t halt_reg; /* halt register */
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uint32_t halt_check_type;
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bool halt_check_voted; /* whether to delay when waiting */
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};
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extern int qcom_clk_branch2_register(struct clkdom *clkdom,
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struct qcom_clk_branch2_def *clkdef);
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#endif /* __QCOM_CLK_BRANCH2_H__ */
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