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8673e05a9a
1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
431 lines
12 KiB
C
431 lines
12 KiB
C
/**************************************************************************
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**
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** $Id: pcisupport.c,v 1.12 1995/03/17 04:27:20 davidg Exp $
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**
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** Device driver for DEC/INTEL PCI chipsets.
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**
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** FreeBSD
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**
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**-------------------------------------------------------------------------
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**
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** Written for FreeBSD by
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** wolf@cologne.de Wolfgang Stanglmeier
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** se@mi.Uni-Koeln.de Stefan Esser
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**
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**-------------------------------------------------------------------------
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**
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** Copyright (c) 1994,1995 Stefan Esser. All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without
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** modification, are permitted provided that the following conditions
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** are met:
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** 1. Redistributions of source code must retain the above copyright
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** notice, this list of conditions and the following disclaimer.
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** 2. Redistributions in binary form must reproduce the above copyright
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** notice, this list of conditions and the following disclaimer in the
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** documentation and/or other materials provided with the distribution.
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** 3. The name of the author may not be used to endorse or promote products
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** derived from this software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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***************************************************************************
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*/
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#define __PCISUPPORT_C__ "pl4 95/03/21"
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/devconf.h>
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#include <machine/cpu.h>
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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/*---------------------------------------------------------
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**
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** Intel chipsets for 486 / Pentium processor
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**
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**---------------------------------------------------------
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*/
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static char* chipset_probe (pcici_t tag, pcidi_t type);
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static void chipset_attach(pcici_t tag, int unit);
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static u_long chipset_count;
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struct pci_device chipset_device = {
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"chip",
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chipset_probe,
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chipset_attach,
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&chipset_count,
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NULL
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};
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DATA_SET (pcidevice_set, chipset_device);
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struct condmsg {
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unsigned char port;
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unsigned char mask;
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unsigned char value;
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char flags;
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char *text;
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};
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static char*
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chipset_probe (pcici_t tag, pcidi_t type)
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{
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u_long data;
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switch (type) {
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case 0x04848086:
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return ("Intel 82378IB PCI-ISA bridge");
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case 0x04838086:
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return ("Intel 82424ZX cache DRAM controller");
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case 0x04828086:
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return ("Intel 82375EB PCI-EISA bridge");
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case 0x04a38086:
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return ("Intel 82434LX PCI cache memory controller");
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case 0x00011011:
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return ("DEC 21050 PCI-PCI bridge");
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};
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/*
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** check classes
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*/
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data = pci_conf_read(tag, PCI_CLASS_REG);
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switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) {
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case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI:
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return ("PCI-PCI bridge");
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};
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return ((char*)0);
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}
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#define M_EQ 0 /* mask and return true if equal */
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#define M_NE 1 /* mask and return true if not equal */
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#define TRUE 2 /* don't read config, always true */
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static const struct condmsg conf82424zx[] =
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{
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{ 0x00, 0x00, 0x00, TRUE, "\tCPU: " },
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{ 0x50, 0xe0, 0x00, M_EQ, "486DX" },
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{ 0x50, 0xe0, 0x20, M_EQ, "486SX" },
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{ 0x50, 0xe0, 0x40, M_EQ, "486DX2 or 486DX4" },
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{ 0x50, 0xe0, 0x80, M_EQ, "Overdrive (writeback)" },
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{ 0x00, 0x00, 0x00, TRUE, ", bus=" },
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{ 0x50, 0x03, 0x00, M_EQ, "25MHz" },
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{ 0x50, 0x03, 0x01, M_EQ, "33MHz" },
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{ 0x53, 0x01, 0x01, TRUE, ", CPU->Memory posting "},
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{ 0x53, 0x01, 0x00, M_EQ, "OFF" },
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{ 0x53, 0x01, 0x01, M_EQ, "ON" },
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{ 0x56, 0x30, 0x00, M_NE, "\n\tWarning:" },
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{ 0x56, 0x20, 0x00, M_NE, " NO cache parity!" },
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{ 0x56, 0x10, 0x00, M_NE, " NO DRAM parity!" },
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{ 0x55, 0x04, 0x04, M_EQ, "\n\tWarning: refresh OFF! " },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tCache: " },
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{ 0x52, 0x01, 0x00, M_EQ, "None" },
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{ 0x52, 0xc1, 0x01, M_EQ, "64KB" },
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{ 0x52, 0xc1, 0x41, M_EQ, "128KB" },
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{ 0x52, 0xc1, 0x81, M_EQ, "256KB" },
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{ 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
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{ 0x52, 0x03, 0x01, M_EQ, " writethrough" },
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{ 0x52, 0x03, 0x03, M_EQ, " writeback" },
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{ 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
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{ 0x52, 0x05, 0x01, M_EQ, "3-1-1-1" },
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{ 0x52, 0x05, 0x05, M_EQ, "2-1-1-1" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tDRAM:" },
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{ 0x55, 0x43, 0x00, M_NE, " page mode" },
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{ 0x55, 0x02, 0x02, M_EQ, " code fetch" },
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{ 0x55, 0x43, 0x43, M_EQ, "," },
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{ 0x55, 0x43, 0x42, M_EQ, " and" },
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{ 0x55, 0x40, 0x40, M_EQ, " read" },
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{ 0x55, 0x03, 0x03, M_EQ, " and" },
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{ 0x55, 0x43, 0x41, M_EQ, " and" },
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{ 0x55, 0x01, 0x01, M_EQ, " write" },
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{ 0x55, 0x43, 0x00, M_NE, "," },
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{ 0x00, 0x00, 0x00, TRUE, " memory clocks=" },
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{ 0x55, 0x20, 0x00, M_EQ, "X-2-2-2" },
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{ 0x55, 0x20, 0x20, M_EQ, "X-1-2-1" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tCPU->PCI: posting " },
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{ 0x53, 0x02, 0x00, M_NE, "ON" },
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{ 0x53, 0x02, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, ", burst mode " },
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{ 0x54, 0x02, 0x00, M_NE, "ON" },
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{ 0x54, 0x02, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tPCI->Memory: posting " },
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{ 0x54, 0x01, 0x00, M_NE, "ON" },
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{ 0x54, 0x01, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, "\n" },
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/* end marker */
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{ 0 }
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};
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static const struct condmsg conf82434lx[] =
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{
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{ 0x00, 0x00, 0x00, TRUE, "\tCPU: " },
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{ 0x50, 0xe3, 0x82, M_EQ, "Pentium, 60MHz" },
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{ 0x50, 0xe3, 0x83, M_EQ, "Pentium, 66MHz" },
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{ 0x50, 0xe3, 0xa2, M_EQ, "Pentium, 90MHz" },
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{ 0x50, 0xe3, 0xa3, M_EQ, "Pentium, 100MHz" },
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{ 0x50, 0xc2, 0x82, M_NE, "(unknown)" },
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{ 0x50, 0x04, 0x00, M_EQ, " (primary cache OFF)" },
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{ 0x53, 0x01, 0x01, TRUE, ", CPU->Memory posting "},
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{ 0x53, 0x01, 0x01, M_NE, "OFF" },
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{ 0x53, 0x01, 0x01, M_EQ, "ON" },
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{ 0x53, 0x04, 0x00, M_NE, ", read around write"},
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{ 0x71, 0xc0, 0x00, M_NE, "\n\tWarning: NO cache parity!" },
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{ 0x57, 0x20, 0x00, M_NE, "\n\tWarning: NO DRAM parity!" },
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{ 0x55, 0x01, 0x01, M_EQ, "\n\tWarning: refresh OFF! " },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tCache: " },
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{ 0x52, 0x01, 0x00, M_EQ, "None" },
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{ 0x52, 0x81, 0x01, M_EQ, "" },
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{ 0x52, 0xc1, 0x81, M_EQ, "256KB" },
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{ 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
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{ 0x52, 0x03, 0x01, M_EQ, " writethrough" },
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{ 0x52, 0x03, 0x03, M_EQ, " writeback" },
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{ 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
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{ 0x52, 0x20, 0x00, M_EQ, "3-2-2-2/4-2-2-2" },
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{ 0x52, 0x20, 0x00, M_NE, "3-1-1-1" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tDRAM:" },
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{ 0x57, 0x10, 0x00, M_EQ, " page mode" },
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{ 0x00, 0x00, 0x00, TRUE, " memory clocks=" },
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{ 0x57, 0xc0, 0x00, M_EQ, "X-4-4-4 (70ns)" },
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{ 0x57, 0xc0, 0x40, M_EQ, "X-4-4-4/X-3-3-3 (60ns)" },
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{ 0x57, 0xc0, 0x80, M_EQ, "???" },
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{ 0x57, 0xc0, 0xc0, M_EQ, "X-3-3-3 (50ns)" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tCPU->PCI: posting " },
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{ 0x53, 0x02, 0x02, M_EQ, "ON" },
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{ 0x53, 0x02, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, ", burst mode " },
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{ 0x54, 0x02, 0x00, M_NE, "ON" },
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{ 0x54, 0x02, 0x00, M_EQ, "OFF" },
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{ 0x54, 0x04, 0x00, TRUE, ", PCI clocks=" },
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{ 0x54, 0x04, 0x00, M_EQ, "2-2-2-2" },
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{ 0x54, 0x04, 0x00, M_NE, "2-1-1-1" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tPCI->Memory: posting " },
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{ 0x54, 0x01, 0x00, M_NE, "ON" },
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{ 0x54, 0x01, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, "\n" },
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/* end marker */
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{ 0 }
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};
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static char confread (pcici_t config_id, int port)
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{
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unsigned long portw = port & ~3;
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unsigned long ports = (port - portw) << 3;
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unsigned long l = pci_conf_read (config_id, portw);
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return (l >> ports);
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}
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static void
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writeconfig (pcici_t config_id, const struct condmsg *tbl)
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{
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while (tbl->text) {
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int cond = 0;
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if (tbl->flags == TRUE) {
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cond = 1;
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} else {
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unsigned char v = (unsigned char) confread(config_id, tbl->port);
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switch (tbl->flags) {
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case M_EQ:
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if ((v & tbl->mask) == tbl->value) cond = 1;
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break;
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case M_NE:
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if ((v & tbl->mask) != tbl->value) cond = 1;
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break;
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}
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}
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if (cond) printf ("%s", tbl->text);
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tbl++;
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}
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}
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static void
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chipset_attach (pcici_t config_id, int unit)
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{
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if (!bootverbose)
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return;
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switch (pci_conf_read (config_id, PCI_ID_REG)) {
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case 0x04838086:
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writeconfig (config_id, conf82424zx);
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break;
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case 0x04a38086:
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writeconfig (config_id, conf82434lx);
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break;
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case 0x04848086:
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case 0x04828086:
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printf ("\t[40] %lx [50] %lx [54] %lx\n",
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pci_conf_read (config_id, 0x40),
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pci_conf_read (config_id, 0x50),
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pci_conf_read (config_id, 0x54));
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break;
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};
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}
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/*---------------------------------------------------------
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**
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** Catchall driver for VGA devices
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**
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** By Garrett Wollman
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** <wollman@halloran-eldar.lcs.mit.edu>
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**
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**---------------------------------------------------------
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*/
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static char* vga_probe (pcici_t tag, pcidi_t type);
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static void vga_attach (pcici_t tag, int unit);
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static u_long vga_count;
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struct pci_device vga_device = {
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"vga",
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vga_probe,
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vga_attach,
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&vga_count,
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NULL
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};
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DATA_SET (pcidevice_set, vga_device);
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static char* vga_probe (pcici_t tag, pcidi_t type)
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{
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int data = pci_conf_read(tag, PCI_CLASS_REG);
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switch (data & PCI_CLASS_MASK) {
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case PCI_CLASS_PREHISTORIC:
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if ((data & PCI_SUBCLASS_MASK)
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!= PCI_SUBCLASS_PREHISTORIC_VGA)
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break;
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case PCI_CLASS_DISPLAY:
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if ((data & PCI_SUBCLASS_MASK)
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== PCI_SUBCLASS_DISPLAY_VGA)
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return "VGA-compatible display device";
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else
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return ("Display device");
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};
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return ((char*)0);
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}
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static void vga_attach (pcici_t tag, int unit)
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{
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/*
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** If the assigned addresses are remapped,
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** the console driver has to be informed about the new address.
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*/
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#if 0
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vm_offset_t va;
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vm_offset_t pa;
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int reg;
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for (reg = PCI_MAP_REG_START; reg < PCI_MAP_REG_END; reg += 4)
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(void) pci_map_mem (tag, reg, &va, &pa);
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#endif
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}
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/*---------------------------------------------------------
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**
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** Hook for loadable pci drivers
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**
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**---------------------------------------------------------
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*/
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static char* lkm_probe (pcici_t tag, pcidi_t type);
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static void lkm_attach (pcici_t tag, int unit);
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static u_long lkm_count;
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struct pci_device lkm_device = {
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"lkm",
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lkm_probe,
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lkm_attach,
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&lkm_count,
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NULL
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};
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DATA_SET (pcidevice_set, lkm_device);
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static char*
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lkm_probe (pcici_t tag, pcidi_t type)
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{
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/*
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** Not yet!
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** (Should try to load a matching driver)
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*/
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return ((char*)0);
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}
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static void
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lkm_attach (pcici_t tag, int unit)
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{}
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/*---------------------------------------------------------
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**
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** Devices to ignore
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**
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**---------------------------------------------------------
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*/
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static char* ign_probe (pcici_t tag, pcidi_t type);
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static void ign_attach (pcici_t tag, int unit);
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static u_long ign_count;
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struct pci_device ign_device = {
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NULL,
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ign_probe,
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ign_attach,
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&ign_count,
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NULL
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};
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DATA_SET (pcidevice_set, ign_device);
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static char*
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ign_probe (pcici_t tag, pcidi_t type)
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{
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switch (type) {
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case 0x10001042ul: /* wd */
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return ("");
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};
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return ((char*)0);
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}
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static void
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ign_attach (pcici_t tag, int unit)
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{}
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