HardenedBSD/sys/conf
Emmanuel Vadot 3df266dff9 arm64: rockchip: Add proper armclock support
The core clock (armclk) on RockChip SoC is special.
It can derive it's clock from many PLLs but RockChip recommand to do it
from "apll" on old SoC and "npll" on new SoC. The reason for choosing npll
is that it's have less jitter and is more close to the arm core on the SoC.
r333314 added the core clock as a composite clock but due to it's specials
property we need to deal with it differently.
A new rk_clk_armclk type is added for this and it supports only the "npll"
as we don't run on old RockChip SoC that only have the "apll".
It will always reparent to "npll" and set the frequency according to a rate
table that is known to be good.
For now we set the "npll" to the desired frequency and just set the core clk
divider to 1 as its parent it just used for the core clk.
2018-05-23 19:07:03 +00:00
..
config.mk
dtb.mk
files
files.amd64
files.arm
files.arm64 arm64: rockchip: Add proper armclock support 2018-05-23 19:07:03 +00:00
files.i386
files.mips
files.powerpc
files.riscv
files.sparc64
kern.mk
kern.opts.mk
kern.post.mk
kern.pre.mk
kmod_syms_prefix.awk
kmod_syms.awk
kmod.mk
ldscript.amd64
ldscript.arm
ldscript.arm64
ldscript.i386
ldscript.mips
ldscript.mips.cfe
ldscript.mips.mips64
ldscript.mips.octeon1
ldscript.powerpc
ldscript.powerpc64
ldscript.powerpcspe
ldscript.riscv
ldscript.sparc64
Makefile.amd64
Makefile.arm
Makefile.arm64
Makefile.i386
Makefile.mips
Makefile.powerpc
Makefile.riscv
Makefile.sparc64
makeLINT.mk
makeLINT.sed
newvers.sh
NOTES
options
options.amd64
options.arm
options.arm64
options.i386
options.mips
options.powerpc
options.riscv
options.sparc64
systags.sh
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