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93 lines
3.4 KiB
C
93 lines
3.4 KiB
C
/*-
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* Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _MACHINE_DB_MACHDEP_H_
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#define _MACHINE_DB_MACHDEP_H_
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#include <machine/riscvreg.h>
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#include <machine/frame.h>
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#include <machine/trap.h>
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#define T_BREAKPOINT (SCAUSE_BREAKPOINT)
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#define T_WATCHPOINT (0)
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typedef vm_offset_t db_addr_t;
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typedef long db_expr_t;
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#define PC_REGS() ((db_addr_t)kdb_frame->tf_sepc)
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#define BKPT_INST (0x00100073)
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#define BKPT_SIZE (INSN_SIZE)
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#define BKPT_SET(inst) (BKPT_INST)
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#define BKPT_SKIP do { \
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uint32_t _instr; \
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\
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_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \
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if ((_instr & 0x3) == 0x3) \
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kdb_frame->tf_sepc += 4; /* ebreak */ \
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else \
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kdb_frame->tf_sepc += 2; /* c.ebreak */ \
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} while (0)
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#define db_clear_single_step kdb_cpu_clear_singlestep
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#define db_set_single_step kdb_cpu_set_singlestep
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#define IS_BREAKPOINT_TRAP(type, code) (type == T_BREAKPOINT)
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#define IS_WATCHPOINT_TRAP(type, code) (type == T_WATCHPOINT)
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#define inst_trap_return(ins) (ins == 0x10000073) /* eret */
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#define inst_return(ins) (ins == 0x00008067) /* ret */
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#define inst_call(ins) (((ins) & 0x7f) == 111 || \
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((ins) & 0x7f) == 103) /* jal, jalr */
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#define inst_load(ins) ({ \
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uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \
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is_load_instr(tmp_instr); \
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})
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#define inst_store(ins) ({ \
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uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \
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is_store_instr(tmp_instr); \
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})
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#define is_load_instr(ins) (((ins) & 0x7f) == 3)
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#define is_store_instr(ins) (((ins) & 0x7f) == 35)
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#define next_instr_address(pc, bd) ((bd) ? (pc) : ((pc) + 4))
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#define DB_ELFSIZE 64
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#endif /* !_MACHINE_DB_MACHDEP_H_ */
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