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159 lines
4.5 KiB
C
159 lines
4.5 KiB
C
/*-
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* Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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#define CPUCFG_BASE 0x01c25c00
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#define CPUCFG_SIZE 0x400
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#define CPU0_RST_CTL 0x40
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#define CPU0_CTL 0x44
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#define CPU0_STATUS 0x48
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#define CPU1_RST_CTL 0x80
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#define CPU1_CTL 0x84
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#define CPU1_STATUS 0x88
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#define CPUCFG_GENCTL 0x184
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#define CPUCFG_P_REG0 0x1a4
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#define CPU1_PWR_CLAMP 0x1b0
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#define CPU1_PWROFF_REG 0x1b4
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#define CPUCFG_DBGCTL0 0x1e0
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#define CPUCFG_DBGCTL1 0x1e4
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void
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platform_mp_init_secondary(void)
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{
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gic_init_secondary();
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}
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void
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platform_mp_setmaxid(void)
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{
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int ncpu;
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if (mp_ncpus != 0)
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return;
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/* Read current CP15 Cache Size ID Register */
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__asm __volatile("mrc p15, 1, %0, c9, c0, 2" : "=r" (ncpu));
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ncpu = ((ncpu >> 24) & 0x3) + 1;
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mp_ncpus = ncpu;
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mp_maxid = ncpu - 1;
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}
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int
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platform_mp_probe(void)
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{
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if (mp_ncpus == 0)
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platform_mp_setmaxid();
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return (mp_ncpus > 1);
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}
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void
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platform_mp_start_ap(void)
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{
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bus_space_handle_t cpucfg;
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uint32_t val;
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if (bus_space_map(fdtbus_bs_tag, CPUCFG_BASE, CPUCFG_SIZE, 0,
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&cpucfg) != 0)
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panic("Couldn't map the CPUCFG\n");
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_P_REG0,
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pmap_kextract((vm_offset_t)mpentry));
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/*
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* Assert nCOREPORESET low and set L1RSTDISABLE low.
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* Ensure DBGPWRDUP is set to LOW to prevent any external
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* debug access to the processor.
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*/
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_RST_CTL, 0);
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/* Set L1RSTDISABLE low */
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val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_GENCTL);
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val &= ~(1 << 1);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_GENCTL, val);
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/* Set DBGPWRDUP low */
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val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1);
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val &= ~(1 << 1);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1, val);
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/* Release power clamp */
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0xff);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x7f);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x3f);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x1f);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x0f);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x07);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x03);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x01);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x00);
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DELAY(10000);
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/* Clear power-off gating */
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val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPU1_PWROFF_REG);
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val &= ~(1 << 0);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWROFF_REG, val);
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DELAY(1000);
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/* De-assert cpu core reset */
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_RST_CTL, 3);
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/* Assert DBGPWRDUP signal */
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val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1);
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val |= (1 << 1);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1, val);
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armv7_sev();
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bus_space_unmap(fdtbus_bs_tag, cpucfg, CPUCFG_SIZE);
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}
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void
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platform_ipi_send(cpuset_t cpus, u_int ipi)
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{
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pic_ipi_send(cpus, ipi);
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}
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