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https://git.hardenedbsd.org/hardenedbsd/HardenedBSD.git
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143 lines
3.7 KiB
Plaintext
143 lines
3.7 KiB
Plaintext
/*-
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* Copyright (c) 2011 The FreeBSD Foundation
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* All rights reserved.
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*
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* Developed by Damjan Marion <damjan.marion@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/dts-v1/;
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/ {
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model = "CompuLab TrimSlice";
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compatible = "compulab,trimslice", "nvidia,tegra20";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&GIC>;
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aliases {
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serial0 = &serial0;
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soc = &SOC;
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};
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memory {
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device_type = "memory";
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reg = < 0x00000000 0x40000000 >; /* 1GB RAM at 0x0 */
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};
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SOC: tegra20@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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bus-frequency = <0>;
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GIC: interrupt-controller@50041000 {
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compatible = "arm,gic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = < 0x50041000 0x1000 >, /* Distributor Registers */
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< 0x50040100 0x0100 >; /* CPU Interface Registers */
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};
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mp_tmr@50040200 {
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compatible = "arm,mpcore-timers";
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clock-frequency = < 50040200 >;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = < 0x50040200 0x100 >, /* Global Timer Registers */
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< 0x50040600 0x100 >; /* Private Timer Registers */
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interrupts = < 27 29 >;
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interrupt-parent = < &GIC >;
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};
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tmr1@60005000 {
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compatible = "nvidia,tegra2-timer";
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reg = <0x60005000 0x8>;
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interrupts = < 32 >;
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interrupt-parent = <&GIC>;
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};
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tmr2@60005008 {
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compatible = "nvidia,tegra2-timer";
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reg = <0x60005008 0x8>;
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interrupts = < 33 >;
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interrupt-parent = <&GIC>;
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};
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tmrus@60005010 {
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compatible = "nvidia,tegra2-timestamp";
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reg = <0x60005010 0x8>;
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};
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tmr3@60005050 {
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compatible = "nvidia,tegra2-timer";
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reg = <0x60005050 0x8>;
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interrupts = < 73 >;
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interrupt-parent = <&GIC>;
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};
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tmr4@60005058 {
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compatible = "nvidia,tegra2-timer";
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reg = <0x60005058 0x8>;
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interrupts = < 74 >;
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interrupt-parent = <&GIC>;
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};
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serial0: serial@70006000 {
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compatible = "ns16550";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = < 68 >;
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interrupt-parent = <&GIC>;
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clock-frequency = < 215654400 >;
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};
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serial1: serial@70006040 {
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compatible = "ns16550";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = < 69 >;
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interrupt-parent = <&GIC>;
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clock-frequency = < 215654400 >;
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};
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serial2: serial@70006200 {
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compatible = "ns16550";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = < 78 >;
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interrupt-parent = <&GIC>;
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clock-frequency = < 215654400 >;
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};
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};
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chosen {
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stdin = "serial0";
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stdout = "serial0";
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};
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};
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