mirror of
https://git.hardenedbsd.org/hardenedbsd/HardenedBSD.git
synced 2024-12-23 10:06:25 +01:00
79 lines
2.6 KiB
Diff
79 lines
2.6 KiB
Diff
Pull in r216989 from upstream llvm trunk (by Renato Golin):
|
|
|
|
MFV: Only emit movw on ARMv6T2+
|
|
|
|
Pull in r216990 from upstream llvm trunk (by Renato Golin):
|
|
|
|
Missing test from r216989
|
|
|
|
Building for the FreeBSD default target ARMv6 was emitting movw ASM on certain
|
|
test cases (found building qmake4/5 for ARM). Don't do that, moreover, the AS
|
|
in base doesn't understand this instruction for this target. One would need
|
|
to use --integrated-as to get this to build if desired.
|
|
|
|
Introduced here: http://svnweb.freebsd.org/changeset/base/271025
|
|
|
|
Index: lib/Target/ARM/ARMInstrInfo.td
|
|
===================================================================
|
|
--- lib/Target/ARM/ARMInstrInfo.td
|
|
+++ lib/Target/ARM/ARMInstrInfo.td
|
|
@@ -3419,7 +3419,8 @@ def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$im
|
|
def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
|
|
(SBCri GPR:$src, so_imm_not:$imm)>;
|
|
def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
|
|
- (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
|
|
+ (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
|
|
+ Requires<[IsARM, HasV6T2]>;
|
|
|
|
// Note: These are implemented in C++ code, because they have to generate
|
|
// ADD/SUBrs instructions, which use a complex pattern that a xform function
|
|
Index: test/CodeGen/ARM/carry.ll
|
|
===================================================================
|
|
--- test/CodeGen/ARM/carry.ll
|
|
+++ test/CodeGen/ARM/carry.ll
|
|
@@ -1,4 +1,4 @@
|
|
-; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
|
|
+; RUN: llc < %s -mtriple=armv6t2-eabi | FileCheck %s
|
|
|
|
define i64 @f1(i64 %a, i64 %b) {
|
|
; CHECK-LABEL: f1:
|
|
Index: test/CodeGen/ARM/pr18364-movw.ll
|
|
===================================================================
|
|
--- test/CodeGen/ARM/pr18364-movw.ll
|
|
+++ test/CodeGen/ARM/pr18364-movw.ll
|
|
@@ -0,0 +1,34 @@
|
|
+; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V5
|
|
+; RUN: llc < %s -mtriple=armv6 | FileCheck %s --check-prefix=V6
|
|
+; RUN: llc < %s -mtriple=armv6t2 | FileCheck %s --check-prefix=V6T2
|
|
+; RUN: llc < %s -mtriple=armv7 | FileCheck %s --check-prefix=V7
|
|
+; PR18364
|
|
+
|
|
+define i64 @f() #0 {
|
|
+entry:
|
|
+; V5-NOT: movw
|
|
+; V6-NOT: movw
|
|
+; V6T2: movw
|
|
+; V7: movw
|
|
+ %y = alloca i64, align 8
|
|
+ %z = alloca i64, align 8
|
|
+ store i64 1, i64* %y, align 8
|
|
+ store i64 11579764786944, i64* %z, align 8
|
|
+ %0 = load i64* %y, align 8
|
|
+ %1 = load i64* %z, align 8
|
|
+ %sub = sub i64 %0, %1
|
|
+ ret i64 %sub
|
|
+}
|
|
+
|
|
+define i64 @g(i64 %a, i32 %b) #0 {
|
|
+entry:
|
|
+; V5-NOT: movw
|
|
+; V6-NOT: movw
|
|
+; V6T2: movw
|
|
+; V7: movw
|
|
+ %0 = mul i64 %a, 86400000
|
|
+ %mul = add i64 %0, -210866803200000
|
|
+ %conv = sext i32 %b to i64
|
|
+ %add = add nsw i64 %mul, %conv
|
|
+ ret i64 %add
|
|
+}
|