mirror of
https://git.hardenedbsd.org/hardenedbsd/HardenedBSD.git
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168 lines
4.6 KiB
C
168 lines
4.6 KiB
C
/*
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* This file is _NOT_ automatically generated. It must agree with the
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* Virtual Function register map definitions in t4vf_defs.h in the common
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* code.
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*/
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struct reg_info t4vf_sge_regs[] = {
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{ "SGE_KDOORBELL", 0x000, 0 },
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{ "QID", 15, 17 },
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{ "Priority", 14, 1 },
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{ "PIDX", 0, 14 },
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{ "SGE_GTS", 0x004, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ NULL, 0, 0 }
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};
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struct reg_info t5vf_sge_regs[] = {
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{ "SGE_VF_KDOORBELL", 0x000, 0 },
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{ "QID", 15, 17 },
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{ "Priority", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_VF_GTS", 0x004, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ NULL, 0, 0 }
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};
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struct reg_info t4vf_mps_regs[] = {
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{ "MPS_VF_CTL", 0x100, 0 },
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{ "TxEn", 1, 1 },
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{ "RxEn", 0, 1 },
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{ "MPS_VF_STAT_TX_VF_BCAST_BYTES_L", 0x180, 0 },
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{ "MPS_VF_STAT_TX_VF_BCAST_BYTES_H", 0x184, 0 },
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{ "MPS_VF_STAT_TX_VF_BCAST_FRAMES_L", 0x188, 0 },
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{ "MPS_VF_STAT_TX_VF_BCAST_FRAMES_H", 0x18c, 0 },
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{ "MPS_VF_STAT_TX_VF_MCAST_BYTES_L", 0x190, 0 },
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{ "MPS_VF_STAT_TX_VF_MCAST_BYTES_H", 0x194, 0 },
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{ "MPS_VF_STAT_TX_VF_MCAST_FRAMES_L", 0x198, 0 },
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{ "MPS_VF_STAT_TX_VF_MCAST_FRAMES_H", 0x19c, 0 },
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{ "MPS_VF_STAT_TX_VF_UCAST_BYTES_L", 0x1a0, 0 },
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{ "MPS_VF_STAT_TX_VF_UCAST_BYTES_H", 0x1a4, 0 },
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{ "MPS_VF_STAT_TX_VF_UCAST_FRAMES_L", 0x1a8, 0 },
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{ "MPS_VF_STAT_TX_VF_UCAST_FRAMES_H", 0x1ac, 0 },
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{ "MPS_VF_STAT_TX_VF_DROP_FRAMES_L", 0x1b0, 0 },
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{ "MPS_VF_STAT_TX_VF_DROP_FRAMES_H", 0x1b4, 0 },
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{ "MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L", 0x1b8, 0 },
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{ "MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H", 0x1bc, 0 },
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{ "MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L", 0x1c0, 0 },
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{ "MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H", 0x1c4, 0 },
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{ "MPS_VF_STAT_RX_VF_BCAST_BYTES_L", 0x1c8, 0 },
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{ "MPS_VF_STAT_RX_VF_BCAST_BYTES_H", 0x1cc, 0 },
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{ "MPS_VF_STAT_RX_VF_BCAST_FRAMES_L", 0x1d0, 0 },
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{ "MPS_VF_STAT_RX_VF_BCAST_FRAMES_H", 0x1d4, 0 },
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{ "MPS_VF_STAT_RX_VF_MCAST_BYTES_L", 0x1d8, 0 },
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{ "MPS_VF_STAT_RX_VF_MCAST_BYTES_H", 0x1dc, 0 },
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{ "MPS_VF_STAT_RX_VF_MCAST_FRAMES_L", 0x1e0, 0 },
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{ "MPS_VF_STAT_RX_VF_MCAST_FRAMES_H", 0x1e4, 0 },
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{ "MPS_VF_STAT_RX_VF_UCAST_BYTES_L", 0x1e8, 0 },
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{ "MPS_VF_STAT_RX_VF_UCAST_BYTES_H", 0x1ec, 0 },
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{ "MPS_VF_STAT_RX_VF_UCAST_FRAMES_L", 0x1f0, 0 },
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{ "MPS_VF_STAT_RX_VF_UCAST_FRAMES_H", 0x1f4, 0 },
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{ "MPS_VF_STAT_RX_VF_ERR_FRAMES_L", 0x1f8, 0 },
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{ "MPS_VF_STAT_RX_VF_ERR_FRAMES_H", 0x1fc, 0 },
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{ NULL, 0, 0 }
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};
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struct reg_info t4vf_pl_regs[] = {
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{ "PL_VF_WHOAMI", 0x200, 0 },
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{ "PortxMap", 24, 3 },
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{ "SourceBus", 16, 2 },
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{ "SourcePF", 8, 3 },
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{ "IsVF", 7, 1 },
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{ "VFID", 0, 7 },
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{ NULL, 0, 0 }
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};
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struct reg_info t5vf_pl_regs[] = {
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{ "PL_WHOAMI", 0x200, 0 },
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{ "PortxMap", 24, 3 },
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{ "SourceBus", 16, 2 },
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{ "SourcePF", 8, 3 },
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{ "IsVF", 7, 1 },
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{ "VFID", 0, 7 },
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{ "PL_VF_REV", 0x204, 0 },
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{ "ChipID", 4, 4 },
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{ "Rev", 0, 4 },
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{ "PL_VF_REVISION", 0x208, 0 },
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{ NULL, 0, 0 }
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};
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struct reg_info t6vf_pl_regs[] = {
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{ "PL_WHOAMI", 0x200, 0 },
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{ "PortxMap", 24, 3 },
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{ "SourceBus", 16, 2 },
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{ "SourcePF", 9, 3 },
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{ "IsVF", 8, 1 },
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{ "VFID", 0, 8 },
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{ "PL_VF_REV", 0x204, 0 },
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{ "ChipID", 4, 4 },
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{ "Rev", 0, 4 },
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{ "PL_VF_REVISION", 0x208, 0 },
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{ NULL, 0, 0 }
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};
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struct reg_info t4vf_cim_regs[] = {
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/*
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* Note: the Mailbox Control register has read side-effects so
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* the driver simply returns 0xffff for this register.
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*/
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{ "CIM_VF_EXT_MAILBOX_CTRL", 0x300, 0 },
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{ "MBGeneric", 4, 4 },
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{ "MBMsgValid", 3, 1 },
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{ "MBIntReq", 2, 1 },
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{ "MBOwner", 0, 2 },
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{ "CIM_VF_EXT_MAILBOX_STATUS", 0x304, 0 },
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{ "MBVFReady", 0, 1 },
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{ NULL, 0, 0 }
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};
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struct reg_info t4vf_mbdata_regs[] = {
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{ "CIM_VF_EXT_MAILBOX_DATA_00", 0x240, 0 },
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{ "Return", 8, 8 },
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{ "Length16", 0, 8 },
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{ "CIM_VF_EXT_MAILBOX_DATA_04", 0x244, 0 },
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{ "OpCode", 24, 8 },
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{ "Request", 23, 1 },
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{ "Read", 22, 1 },
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{ "Write", 21, 1 },
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{ "Execute", 20, 1 },
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{ "CIM_VF_EXT_MAILBOX_DATA_08", 0x248, 0 },
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{ "CIM_VF_EXT_MAILBOX_DATA_0c", 0x24c, 0 },
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{ "CIM_VF_EXT_MAILBOX_DATA_10", 0x250, 0 },
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{ "CIM_VF_EXT_MAILBOX_DATA_14", 0x254, 0 },
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{ "CIM_VF_EXT_MAILBOX_DATA_18", 0x258, 0 },
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{ "CIM_VF_EXT_MAILBOX_DATA_1c", 0x25c, 0 },
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{ "CIM_VF_EXT_MAILBOX_DATA_20", 0x260, 0 },
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{ "CIM_VF_EXT_MAILBOX_DATA_24", 0x264, 0 },
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{ "CIM_VF_EXT_MAILBOX_DATA_28", 0x268, 0 },
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{ "CIM_VF_EXT_MAILBOX_DATA_2c", 0x26c, 0 },
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{ "CIM_VF_EXT_MAILBOX_DATA_30", 0x270, 0 },
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{ "CIM_VF_EXT_MAILBOX_DATA_34", 0x274, 0 },
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{ "CIM_VF_EXT_MAILBOX_DATA_38", 0x278, 0 },
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{ "CIM_VF_EXT_MAILBOX_DATA_3c", 0x27c, 0 },
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{ NULL, 0, 0 }
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};
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