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240 lines
8.5 KiB
C
240 lines
8.5 KiB
C
/*-
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* Copyright (c) 2016-2021, Mellanox Technologies, Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __MLX5_PORT_H__
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#define __MLX5_PORT_H__
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#include <dev/mlx5/driver.h>
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enum mlx5_beacon_duration {
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MLX5_BEACON_DURATION_OFF = 0x0,
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MLX5_BEACON_DURATION_INF = 0xffff,
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};
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enum mlx5_module_id {
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MLX5_MODULE_ID_SFP = 0x3,
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MLX5_MODULE_ID_QSFP = 0xC,
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MLX5_MODULE_ID_QSFP_PLUS = 0xD,
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MLX5_MODULE_ID_QSFP28 = 0x11,
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};
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enum mlx5_an_status {
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MLX5_AN_UNAVAILABLE = 0,
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MLX5_AN_COMPLETE = 1,
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MLX5_AN_FAILED = 2,
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MLX5_AN_LINK_UP = 3,
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MLX5_AN_LINK_DOWN = 4,
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};
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/* EEPROM I2C Addresses */
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#define MLX5_I2C_ADDR_LOW 0x50
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#define MLX5_I2C_ADDR_HIGH 0x51
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#define MLX5_EEPROM_PAGE_LENGTH 256
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#define MLX5_EEPROM_MAX_BYTES 32
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#define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff
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#define MLX5_EEPROM_REVISION_ID_BYTE_MASK 0x0000ff00
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#define MLX5_EEPROM_PAGE_3_VALID_BIT_MASK 0x00040000
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#define MLX5_EEPROM_LOW_PAGE 0x0
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#define MLX5_EEPROM_HIGH_PAGE 0x3
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#define MLX5_EEPROM_HIGH_PAGE_OFFSET 128
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#define MLX5_EEPROM_INFO_BYTES 0x3
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/* EEPROM Standards for plug in modules */
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#ifndef MLX5_ETH_MODULE_SFF_8472
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#define MLX5_ETH_MODULE_SFF_8472 0x1
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#define MLX5_ETH_MODULE_SFF_8472_LEN 128
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#endif
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#ifndef MLX5_ETH_MODULE_SFF_8636
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#define MLX5_ETH_MODULE_SFF_8636 0x2
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#define MLX5_ETH_MODULE_SFF_8636_LEN 256
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#endif
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#ifndef MLX5_ETH_MODULE_SFF_8436
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#define MLX5_ETH_MODULE_SFF_8436 0x3
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#define MLX5_ETH_MODULE_SFF_8436_LEN 256
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#endif
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enum mlx5e_link_speed {
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MLX5E_1000BASE_CX_SGMII = 0,
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MLX5E_1000BASE_KX = 1,
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MLX5E_10GBASE_CX4 = 2,
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MLX5E_10GBASE_KX4 = 3,
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MLX5E_10GBASE_KR = 4,
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MLX5E_20GBASE_KR2 = 5,
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MLX5E_40GBASE_CR4 = 6,
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MLX5E_40GBASE_KR4 = 7,
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MLX5E_56GBASE_R4 = 8,
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MLX5E_10GBASE_CR = 12,
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MLX5E_10GBASE_SR = 13,
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MLX5E_10GBASE_ER_LR = 14,
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MLX5E_40GBASE_SR4 = 15,
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MLX5E_40GBASE_LR4_ER4 = 16,
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MLX5E_50GBASE_SR2 = 18,
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MLX5E_50GBASE_KR4 = 19,
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MLX5E_100GBASE_CR4 = 20,
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MLX5E_100GBASE_SR4 = 21,
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MLX5E_100GBASE_KR4 = 22,
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MLX5E_100GBASE_LR4 = 23,
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MLX5E_100BASE_TX = 24,
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MLX5E_1000BASE_T = 25,
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MLX5E_10GBASE_T = 26,
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MLX5E_25GBASE_CR = 27,
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MLX5E_25GBASE_KR = 28,
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MLX5E_25GBASE_SR = 29,
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MLX5E_50GBASE_CR2 = 30,
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MLX5E_50GBASE_KR2 = 31,
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MLX5E_LINK_SPEEDS_NUMBER = 32,
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};
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enum mlx5e_ext_link_speed {
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MLX5E_SGMII_100M = 0,
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MLX5E_1000BASE_X_SGMII = 1,
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MLX5E_5GBASE_R = 3,
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MLX5E_10GBASE_XFI_XAUI_1 = 4,
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MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5,
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MLX5E_25GAUI_1_25GBASE_CR_KR = 6,
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MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7,
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MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8,
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MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9,
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MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10,
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MLX5E_100GAUI_1_100GBASE_CR_KR = 11,
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MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12,
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MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13,
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MLX5E_400GAUI_8 = 15,
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MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16,
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MLX5E_EXT_LINK_SPEEDS_NUMBER = 32,
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};
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enum mlx5e_cable_type {
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MLX5E_CABLE_TYPE_UNKNOWN = 0,
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MLX5E_CABLE_TYPE_ACTIVE_CABLE = 1,
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MLX5E_CABLE_TYPE_OPTICAL_MODULE = 2,
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MLX5E_CABLE_TYPE_PASSIVE_COPPER = 3,
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MLX5E_CABLE_TYPE_CABLE_UNPLUGGED = 4,
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MLX5E_CABLE_TYPE_TWISTED_PAIR = 5,
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MLX5E_CABLE_TYPE_NUMBER = 8,
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};
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enum mlx5_qpts_trust_state {
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MLX5_QPTS_TRUST_PCP = 1,
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MLX5_QPTS_TRUST_DSCP = 2,
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MLX5_QPTS_TRUST_BOTH = 3,
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};
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struct mlx5e_port_eth_proto {
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u32 cap;
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u32 admin;
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u32 oper;
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};
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#ifndef SPEED_40000
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#define SPEED_40000 40000
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#endif
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#define MLX5E_PROT_MASK(link_mode) (1 << (link_mode))
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#define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
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#define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
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#define MLX5_GET_ETH_PROTO(reg, out, ext, field) \
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((ext) ? MLX5_GET(reg, out, ext_##field) : \
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MLX5_GET(reg, out, field))
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int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
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int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
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int ptys_size, int proto_mask, u8 local_port);
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int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
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u32 *proto_cap, int proto_mask);
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int mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask,
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u8 *an_disable_cap, u8 *an_disable_status);
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int mlx5_set_port_autoneg(struct mlx5_core_dev *dev, bool disable,
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u32 eth_proto_admin, int proto_mask);
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int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
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u32 *proto_admin, int proto_mask);
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int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev,
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u32 *proto_oper, u8 local_port);
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int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
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int proto_mask, bool ext);
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int mlx5_set_port_status(struct mlx5_core_dev *dev,
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enum mlx5_port_status status);
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int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status);
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int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
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enum mlx5_port_status *status);
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int mlx5_set_port_pause_and_pfc(struct mlx5_core_dev *dev, u32 port,
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u8 rx_pause, u8 tx_pause,
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u8 pfc_en_rx, u8 pfc_en_tx);
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int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port,
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u32 *rx_pause, u32 *tx_pause);
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int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx);
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int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu);
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int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu);
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int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu);
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unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num);
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int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num);
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int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num,
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int device_addr, int size, int module_num, u32 *data,
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int *size_read);
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int mlx5_max_tc(struct mlx5_core_dev *mdev);
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int mlx5_query_port_tc_rate_limit(struct mlx5_core_dev *mdev,
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u8 *max_bw_value,
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u8 *max_bw_units);
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int mlx5_modify_port_tc_rate_limit(struct mlx5_core_dev *mdev,
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const u8 *max_bw_value,
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const u8 *max_bw_units);
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int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
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u8 prio, u8 *tc);
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int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, int prio_index,
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const u8 prio_tc);
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int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, const u8 *tc_group);
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int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
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u8 tc, u8 *tc_group);
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int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, const u8 *tc_bw);
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int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *bw_pct);
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int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
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int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
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#define MLX5_MAX_SUPPORTED_DSCP 64
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int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, const u8 *dscp2prio);
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int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
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int mlx5_query_pddr_range_info(struct mlx5_core_dev *mdev, u8 local_port, u8 *is_er_type);
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int mlx5_query_pddr_cable_type(struct mlx5_core_dev *mdev, u8 local_port, u8 *cable_type);
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u32 mlx5e_port_ptys2speed(struct mlx5_core_dev *mdev, u32 eth_proto_oper);
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int mlx5e_port_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
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int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,
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struct mlx5e_port_eth_proto *eproto);
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int mlx5e_port_query_pbmc(struct mlx5_core_dev *mdev, void *out);
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int mlx5e_port_set_pbmc(struct mlx5_core_dev *mdev, void *in);
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int mlx5e_port_query_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer);
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int mlx5e_port_set_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer);
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#endif /* __MLX5_PORT_H__ */
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