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https://git.hardenedbsd.org/hardenedbsd/HardenedBSD.git
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393 lines
9.1 KiB
C
393 lines
9.1 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2013-2014 Qlogic Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* File: qls_isr.c
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* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
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*/
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#include <sys/cdefs.h>
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#include "qls_os.h"
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#include "qls_hw.h"
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#include "qls_def.h"
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#include "qls_inline.h"
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#include "qls_ver.h"
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#include "qls_glbl.h"
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#include "qls_dbg.h"
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static void
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qls_tx_comp(qla_host_t *ha, uint32_t txr_idx, q81_tx_mac_comp_t *tx_comp)
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{
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qla_tx_buf_t *txb;
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uint32_t tx_idx = tx_comp->tid_lo;
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if (tx_idx >= NUM_TX_DESCRIPTORS) {
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ha->qla_initiate_recovery = 1;
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return;
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}
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txb = &ha->tx_ring[txr_idx].tx_buf[tx_idx];
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if (txb->m_head) {
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if_inc_counter(ha->ifp, IFCOUNTER_OPACKETS, 1);
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bus_dmamap_sync(ha->tx_tag, txb->map,
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BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(ha->tx_tag, txb->map);
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m_freem(txb->m_head);
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txb->m_head = NULL;
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}
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ha->tx_ring[txr_idx].txr_done++;
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if (ha->tx_ring[txr_idx].txr_done == NUM_TX_DESCRIPTORS)
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ha->tx_ring[txr_idx].txr_done = 0;
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}
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static void
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qls_replenish_rx(qla_host_t *ha, uint32_t r_idx)
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{
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qla_rx_buf_t *rxb;
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qla_rx_ring_t *rxr;
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int count;
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volatile q81_bq_addr_e_t *sbq_e;
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rxr = &ha->rx_ring[r_idx];
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count = rxr->rx_free;
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sbq_e = rxr->sbq_vaddr;
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while (count--) {
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rxb = &rxr->rx_buf[rxr->sbq_next];
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if (rxb->m_head == NULL) {
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if (qls_get_mbuf(ha, rxb, NULL) != 0) {
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device_printf(ha->pci_dev,
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"%s: qls_get_mbuf [0,%d,%d] failed\n",
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__func__, rxr->sbq_next, r_idx);
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rxb->m_head = NULL;
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break;
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}
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}
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if (rxb->m_head != NULL) {
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sbq_e[rxr->sbq_next].addr_lo = (uint32_t)rxb->paddr;
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sbq_e[rxr->sbq_next].addr_hi =
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(uint32_t)(rxb->paddr >> 32);
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rxr->sbq_next++;
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if (rxr->sbq_next == NUM_RX_DESCRIPTORS)
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rxr->sbq_next = 0;
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rxr->sbq_free++;
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rxr->rx_free--;
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}
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if (rxr->sbq_free == 16) {
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rxr->sbq_in += 16;
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rxr->sbq_in = rxr->sbq_in & (NUM_RX_DESCRIPTORS - 1);
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rxr->sbq_free = 0;
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Q81_WR_SBQ_PROD_IDX(r_idx, (rxr->sbq_in));
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}
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}
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}
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static int
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qls_rx_comp(qla_host_t *ha, uint32_t rxr_idx, uint32_t cq_idx, q81_rx_t *cq_e)
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{
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qla_rx_buf_t *rxb;
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qla_rx_ring_t *rxr;
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device_t dev = ha->pci_dev;
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struct mbuf *mp = NULL;
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if_t ifp = ha->ifp;
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#if defined(INET) || defined(INET6)
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struct lro_ctrl *lro;
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#endif
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struct ether_vlan_header *eh;
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rxr = &ha->rx_ring[rxr_idx];
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#if defined(INET) || defined(INET6)
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lro = &rxr->lro;
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#endif
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rxb = &rxr->rx_buf[rxr->rx_next];
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if (!(cq_e->flags1 & Q81_RX_FLAGS1_DS)) {
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device_printf(dev, "%s: DS bit not set \n", __func__);
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return -1;
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}
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if (rxb->paddr != cq_e->b_paddr) {
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device_printf(dev,
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"%s: (rxb->paddr != cq_e->b_paddr)[%p, %p] \n",
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__func__, (void *)rxb->paddr, (void *)cq_e->b_paddr);
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Q81_SET_CQ_INVALID(cq_idx);
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ha->qla_initiate_recovery = 1;
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return(-1);
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}
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rxr->rx_int++;
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if ((cq_e->flags1 & Q81_RX_FLAGS1_ERR_MASK) == 0) {
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mp = rxb->m_head;
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rxb->m_head = NULL;
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if (mp == NULL) {
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device_printf(dev, "%s: mp == NULL\n", __func__);
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} else {
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mp->m_flags |= M_PKTHDR;
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mp->m_pkthdr.len = cq_e->length;
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mp->m_pkthdr.rcvif = ifp;
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mp->m_len = cq_e->length;
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eh = mtod(mp, struct ether_vlan_header *);
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if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
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uint32_t *data = (uint32_t *)eh;
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mp->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
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mp->m_flags |= M_VLANTAG;
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*(data + 3) = *(data + 2);
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*(data + 2) = *(data + 1);
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*(data + 1) = *data;
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m_adj(mp, ETHER_VLAN_ENCAP_LEN);
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}
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if ((cq_e->flags1 & Q81_RX_FLAGS1_RSS_MATCH_MASK)) {
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rxr->rss_int++;
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mp->m_pkthdr.flowid = cq_e->rss;
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M_HASHTYPE_SET(mp, M_HASHTYPE_OPAQUE_HASH);
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}
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if (cq_e->flags0 & (Q81_RX_FLAGS0_TE |
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Q81_RX_FLAGS0_NU | Q81_RX_FLAGS0_IE)) {
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mp->m_pkthdr.csum_flags = 0;
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} else {
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mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED |
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CSUM_IP_VALID | CSUM_DATA_VALID |
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CSUM_PSEUDO_HDR;
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mp->m_pkthdr.csum_data = 0xFFFF;
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}
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if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
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#if defined(INET) || defined(INET6)
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if (lro->lro_cnt && (tcp_lro_rx(lro, mp, 0) == 0)) {
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/* LRO packet has been successfully queued */
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} else
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#endif
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{
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if_input(ifp, mp);
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}
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}
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} else {
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device_printf(dev, "%s: err [0%08x]\n", __func__, cq_e->flags1);
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}
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rxr->rx_free++;
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rxr->rx_next++;
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if (rxr->rx_next == NUM_RX_DESCRIPTORS)
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rxr->rx_next = 0;
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if ((rxr->rx_free + rxr->sbq_free) >= 16)
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qls_replenish_rx(ha, rxr_idx);
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return 0;
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}
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static void
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qls_cq_isr(qla_host_t *ha, uint32_t cq_idx)
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{
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q81_cq_e_t *cq_e, *cq_b;
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uint32_t i, cq_comp_idx;
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int ret = 0, tx_comp_done = 0;
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#if defined(INET) || defined(INET6)
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struct lro_ctrl *lro = &ha->rx_ring[cq_idx].lro;
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#endif
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cq_b = ha->rx_ring[cq_idx].cq_base_vaddr;
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cq_comp_idx = *(ha->rx_ring[cq_idx].cqi_vaddr);
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i = ha->rx_ring[cq_idx].cq_next;
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while (i != cq_comp_idx) {
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cq_e = &cq_b[i];
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switch (cq_e->opcode) {
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case Q81_IOCB_TX_MAC:
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case Q81_IOCB_TX_TSO:
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qls_tx_comp(ha, cq_idx, (q81_tx_mac_comp_t *)cq_e);
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tx_comp_done++;
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break;
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case Q81_IOCB_RX:
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ret = qls_rx_comp(ha, cq_idx, i, (q81_rx_t *)cq_e);
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break;
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case Q81_IOCB_MPI:
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case Q81_IOCB_SYS:
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default:
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device_printf(ha->pci_dev, "%s[%d %d 0x%x]: illegal \n",
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__func__, i, (*(ha->rx_ring[cq_idx].cqi_vaddr)),
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cq_e->opcode);
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qls_dump_buf32(ha, __func__, cq_e,
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(sizeof (q81_cq_e_t) >> 2));
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break;
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}
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i++;
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if (i == NUM_CQ_ENTRIES)
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i = 0;
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if (ret) {
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break;
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}
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if (i == cq_comp_idx) {
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cq_comp_idx = *(ha->rx_ring[cq_idx].cqi_vaddr);
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}
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if (tx_comp_done) {
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taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
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tx_comp_done = 0;
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}
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}
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#if defined(INET) || defined(INET6)
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tcp_lro_flush_all(lro);
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#endif
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ha->rx_ring[cq_idx].cq_next = cq_comp_idx;
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if (!ret) {
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Q81_WR_CQ_CONS_IDX(cq_idx, (ha->rx_ring[cq_idx].cq_next));
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}
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if (tx_comp_done)
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taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
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return;
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}
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static void
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qls_mbx_isr(qla_host_t *ha)
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{
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uint32_t data;
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int i;
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device_t dev = ha->pci_dev;
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if (qls_mbx_rd_reg(ha, 0, &data) == 0) {
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if ((data & 0xF000) == 0x4000) {
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ha->mbox[0] = data;
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for (i = 1; i < Q81_NUM_MBX_REGISTERS; i++) {
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if (qls_mbx_rd_reg(ha, i, &data))
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break;
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ha->mbox[i] = data;
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}
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ha->mbx_done = 1;
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} else if ((data & 0xF000) == 0x8000) {
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/* we have an AEN */
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ha->aen[0] = data;
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for (i = 1; i < Q81_NUM_AEN_REGISTERS; i++) {
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if (qls_mbx_rd_reg(ha, i, &data))
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break;
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ha->aen[i] = data;
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}
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device_printf(dev,"%s: AEN "
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"[0x%08x 0x%08x 0x%08x 0x%08x 0x%08x"
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" 0x%08x 0x%08x 0x%08x 0x%08x]\n",
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__func__,
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ha->aen[0], ha->aen[1], ha->aen[2],
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ha->aen[3], ha->aen[4], ha->aen[5],
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ha->aen[6], ha->aen[7], ha->aen[8]);
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switch ((ha->aen[0] & 0xFFFF)) {
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case 0x8011:
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ha->link_up = 1;
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break;
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case 0x8012:
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ha->link_up = 0;
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break;
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case 0x8130:
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ha->link_hw_info = ha->aen[1];
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break;
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case 0x8131:
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ha->link_hw_info = 0;
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break;
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}
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}
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}
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WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, Q81_CTL_HCS_CMD_CLR_RTH_INTR);
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return;
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}
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void
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qls_isr(void *arg)
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{
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qla_ivec_t *ivec = arg;
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qla_host_t *ha;
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uint32_t status;
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uint32_t cq_idx;
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device_t dev;
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ha = ivec->ha;
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cq_idx = ivec->cq_idx;
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dev = ha->pci_dev;
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status = READ_REG32(ha, Q81_CTL_STATUS);
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if (status & Q81_CTL_STATUS_FE) {
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device_printf(dev, "%s fatal error\n", __func__);
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return;
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}
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if ((cq_idx == 0) && (status & Q81_CTL_STATUS_PI)) {
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qls_mbx_isr(ha);
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}
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status = READ_REG32(ha, Q81_CTL_INTR_STATUS1);
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if (status & ( 0x1 << cq_idx))
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qls_cq_isr(ha, cq_idx);
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Q81_ENABLE_INTR(ha, cq_idx);
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return;
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}
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