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119 lines
3.0 KiB
Plaintext
119 lines
3.0 KiB
Plaintext
/*-
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* Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/dts-v1/;
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#include "socfpga_arria10_socdk.dtsi"
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/ {
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model = "Altera SOCFPGA Arria 10";
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compatible = "altr,socfpga-arria10", "altr,socfpga";
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/* Reserve first page for secondary CPU trampoline code */
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memreserve = < 0x00000000 0x1000 >;
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soc {
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/* Local timer */
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timer@ffffc600 {
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clock-frequency = <200000000>;
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};
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/* Global timer */
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global_timer: timer@ffffc200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0xffffc200 0x20>;
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interrupts = <1 11 0x301>;
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clock-frequency = <200000000>;
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};
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};
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chosen {
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stdin = "serial1";
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stdout = "serial1";
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};
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};
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&uart1 {
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clock-frequency = < 50000000 >;
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};
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&mmc {
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status = "okay";
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num-slots = <1>;
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cap-sd-highspeed;
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broken-cd;
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bus-width = <4>;
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bus-frequency = <200000000>;
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};
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&i2c1 {
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lcd@28 {
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compatible = "newhaven,nhd-0216k3z-nsw-bbw";
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reg = <0x28>;
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};
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};
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&usb0 {
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dr_mode = "host";
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};
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&qspi {
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status = "okay";
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dmas = <&pdma 24>, <&pdma 25>;
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dma-names = "tx", "rx";
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flash0: n25q00@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q00aa";
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reg = <0>;
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spi-max-frequency = <100000000>;
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m25p,fast-read;
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cdns,page-size = <256>;
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cdns,block-size = <16>;
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cdns,read-delay = <4>;
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cdns,tshsl-ns = <50>;
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cdns,tsd2d-ns = <50>;
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cdns,tchsh-ns = <4>;
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cdns,tslch-ns = <4>;
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partition@qspi-boot {
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label = "boot";
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reg = <0x0 0x2720000>;
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};
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partition@qspi-rootfs {
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label = "rootfs";
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reg = <0x2720000 0x58E0000>;
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};
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};
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};
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