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292 lines
8.1 KiB
C
292 lines
8.1 KiB
C
/*-
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*******************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/**
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* @{
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* @file al_hal_iofic.c
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*
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* @brief interrupt controller hal
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*
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*/
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#include "al_hal_iofic.h"
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#include "al_hal_iofic_regs.h"
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/*
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* configure the interrupt registers, interrupts will are kept masked
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*/
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int al_iofic_config(void __iomem *regs_base, int group, uint32_t flags)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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al_reg_write32(®s->ctrl[group].int_control_grp, flags);
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return 0;
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}
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/*
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* configure the moderation timer resolution for a given group
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*/
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int al_iofic_moder_res_config(void __iomem *regs_base, int group,
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uint8_t resolution)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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uint32_t reg;
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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reg = al_reg_read32(®s->ctrl[group].int_control_grp);
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AL_REG_FIELD_SET(reg,
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INT_CONTROL_GRP_MOD_RES_MASK,
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INT_CONTROL_GRP_MOD_RES_SHIFT,
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resolution);
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al_reg_write32(®s->ctrl[group].int_control_grp, reg);
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return 0;
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}
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/*
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* configure the moderation timer interval for a given legacy interrupt group
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*/
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int al_iofic_legacy_moder_interval_config(void __iomem *regs_base, int group,
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uint8_t interval)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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uint32_t reg;
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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reg = al_reg_read32(®s->ctrl[group].int_control_grp);
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AL_REG_FIELD_SET(reg,
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INT_CONTROL_GRP_MOD_INTV_MASK,
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INT_CONTROL_GRP_MOD_INTV_SHIFT,
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interval);
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al_reg_write32(®s->ctrl[group].int_control_grp, reg);
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return 0;
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}
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/*
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* configure the moderation timer interval for a given msix vector.
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*/
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int al_iofic_msix_moder_interval_config(void __iomem *regs_base, int group,
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uint8_t vector, uint8_t interval)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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uint32_t reg;
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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reg = al_reg_read32(®s->grp_int_mod[group][vector].grp_int_mod_reg);
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AL_REG_FIELD_SET(reg,
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INT_MOD_INTV_MASK,
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INT_MOD_INTV_SHIFT,
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interval);
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al_reg_write32(®s->grp_int_mod[group][vector].grp_int_mod_reg, reg);
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return 0;
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}
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/*
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* configure the target-id attributes for a given msix vector.
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*/
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int al_iofic_msix_tgtid_attributes_config(void __iomem *regs_base, int group,
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uint8_t vector, uint32_t tgtid, uint8_t tgtid_en)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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uint32_t reg = 0;
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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AL_REG_FIELD_SET(reg,
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INT_MSIX_TGTID_MASK,
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INT_MSIX_TGTID_SHIFT,
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tgtid);
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AL_REG_BIT_VAL_SET(reg,
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INT_MSIX_TGTID_EN_SHIFT,
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tgtid_en);
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al_reg_write32(®s->grp_int_mod[group][vector].grp_int_tgtid_reg, reg);
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return 0;
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}
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/*
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* return the offset of the unmask register for a given group
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*/
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uint32_t __iomem * al_iofic_unmask_offset_get(void __iomem *regs_base, int group)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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return ®s->ctrl[group].int_mask_clear_grp;
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}
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/*
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* unmask specific interrupts for a given group
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*/
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void al_iofic_unmask(void __iomem *regs_base, int group, uint32_t mask)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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/*
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* use the mask clear register, no need to read the mask register
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* itself. write 0 to unmask, 1 has no effect
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*/
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al_reg_write32_relaxed(®s->ctrl[group].int_mask_clear_grp, ~mask);
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}
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/*
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* mask specific interrupts for a given group
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*/
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void al_iofic_mask(void __iomem *regs_base, int group, uint32_t mask)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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uint32_t reg;
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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reg = al_reg_read32(®s->ctrl[group].int_mask_grp);
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al_reg_write32(®s->ctrl[group].int_mask_grp, reg | mask);
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}
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/*
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* read the mask for a given group
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*/
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uint32_t al_iofic_read_mask(void __iomem *regs_base, int group)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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return al_reg_read32(®s->ctrl[group].int_mask_grp);
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}
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/*
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* read interrupt cause register for a given group
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*/
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uint32_t al_iofic_read_cause(void __iomem *regs_base, int group)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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return al_reg_read32(®s->ctrl[group].int_cause_grp);
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}
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/*
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* clear bits in the interrupt cause register for a given group
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*/
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void al_iofic_clear_cause(void __iomem *regs_base, int group, uint32_t mask)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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/* inverse mask, writing 1 has no effect */
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al_reg_write32(®s->ctrl[group].int_cause_grp, ~mask);
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}
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/*
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* Set the cause register for a given group
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*/
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void al_iofic_set_cause(void __iomem *regs_base, int group, uint32_t mask)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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al_reg_write32(®s->ctrl[group].int_cause_set_grp, mask);
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}
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/*
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* unmask specific interrupts from aborting the udma a given group
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*/
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void al_iofic_abort_mask(void __iomem *regs_base, int group, uint32_t mask)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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al_reg_write32(®s->ctrl[group].int_abort_msk_grp, mask);
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}
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/*
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* trigger all interrupts that are waiting for moderation timers to expire
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*/
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void al_iofic_interrupt_moderation_reset(void __iomem *regs_base, int group)
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{
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struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
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uint32_t reg = 0;
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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al_assert(regs_base);
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al_assert(group < AL_IOFIC_MAX_GROUPS);
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reg = al_reg_read32(®s->ctrl[group].int_control_grp);
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reg |= INT_CONTROL_GRP_MOD_RST;
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al_reg_write32(®s->ctrl[group].int_control_grp, reg);
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}
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/** @} end of interrupt controller group */
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