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128 lines
4.6 KiB
C
128 lines
4.6 KiB
C
/*_
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********************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __AL_HAL_IOFIC_REG_H
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#define __AL_HAL_IOFIC_REG_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Unit Registers
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*/
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struct al_iofic_grp_ctrl {
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uint32_t int_cause_grp; /* Interrupt Cause RegisterSet by hardware */
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uint32_t rsrvd1;
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uint32_t int_cause_set_grp; /* Interrupt Cause Set RegisterWriting 1 to a bit in t ... */
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uint32_t rsrvd2;
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uint32_t int_mask_grp; /* Interrupt Mask RegisterIf Auto-mask control bit =TR ... */
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uint32_t rsrvd3;
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uint32_t int_mask_clear_grp; /* Interrupt Mask Clear RegisterUsed when auto-mask co ... */
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uint32_t rsrvd4;
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uint32_t int_status_grp; /* Interrupt status RegisterThis register latch the st ... */
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uint32_t rsrvd5;
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uint32_t int_control_grp; /* Interrupt Control Register */
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uint32_t rsrvd6;
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uint32_t int_abort_msk_grp; /* Interrupt Mask RegisterEach bit in this register ma ... */
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uint32_t rsrvd7;
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uint32_t int_log_msk_grp; /* Interrupt Log RegisterEach bit in this register mas ... */
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uint32_t rsrvd8;
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};
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struct al_iofic_grp_mod {
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uint32_t grp_int_mod_reg; /* Interrupt moderation registerDedicated moderation in ... */
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uint32_t grp_int_tgtid_reg;
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};
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struct al_iofic_regs {
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struct al_iofic_grp_ctrl ctrl[0];
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uint32_t rsrvd1[0x400 >> 2];
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struct al_iofic_grp_mod grp_int_mod[0][32];
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};
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/*
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* Registers Fields
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*/
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/**** int_control_grp register ****/
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/* When Clear_on_Read =1, All bits of Cause register ... */
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#define INT_CONTROL_GRP_CLEAR_ON_READ (1 << 0)
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/* (must be set only when MSIX is enabled)When Auto-Ma ... */
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#define INT_CONTROL_GRP_AUTO_MASK (1 << 1)
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/* Auto_Clear (RW)When Auto-Clear =1, the bits in the ... */
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#define INT_CONTROL_GRP_AUTO_CLEAR (1 << 2)
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/* When Set_on_Posedge =1, the bits in the interrupt c ... */
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#define INT_CONTROL_GRP_SET_ON_POSEDGE (1 << 3)
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/* When Moderation_Reset =1, all Moderation timers ass ... */
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#define INT_CONTROL_GRP_MOD_RST (1 << 4)
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/* When mask_msi_x =1, No MSI-X from this group is sen ... */
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#define INT_CONTROL_GRP_MASK_MSI_X (1 << 5)
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/* MSI-X AWID value, same ID for all cause bits */
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#define INT_CONTROL_GRP_AWID_MASK 0x00000F00
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#define INT_CONTROL_GRP_AWID_SHIFT 8
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/* This value determines the interval between interrup ... */
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#define INT_CONTROL_GRP_MOD_INTV_MASK 0x00FF0000
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#define INT_CONTROL_GRP_MOD_INTV_SHIFT 16
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/* This value determines the Moderation_Timer_Clock sp ... */
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#define INT_CONTROL_GRP_MOD_RES_MASK 0x0F000000
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#define INT_CONTROL_GRP_MOD_RES_SHIFT 24
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/**** grp_int_mod_reg register ****/
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/* Interrupt Moderation Interval registerDedicated reg ... */
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#define INT_MOD_INTV_MASK 0x000000FF
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#define INT_MOD_INTV_SHIFT 0
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/**** grp_int_tgtid_reg register ****/
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/* Interrupt tgtid value registerDedicated reg ... */
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#define INT_MSIX_TGTID_MASK 0x0000FFFF
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#define INT_MSIX_TGTID_SHIFT 0
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/* Interrupt tgtid_en value registerDedicated reg ... */
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#define INT_MSIX_TGTID_EN_SHIFT 31
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#ifdef __cplusplus
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}
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#endif
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#endif /* __AL_HAL_IOFIC_REG_H */
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