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420 lines
16 KiB
C
420 lines
16 KiB
C
/*******************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/**
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* @file al_hal_udma_regs_gen.h
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*
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* @brief C Header file for the UDMA general registers
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*
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*/
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#ifndef __AL_HAL_UDMA_GEN_REG_H
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#define __AL_HAL_UDMA_GEN_REG_H
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#include "al_hal_udma_iofic_regs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Unit Registers
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*/
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struct udma_gen_dma_misc {
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/* [0x0] Reserved register for the interrupt controller */
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uint32_t int_cfg;
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/* [0x4] Revision register */
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uint32_t revision;
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/* [0x8] Reserved for future use */
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uint32_t general_cfg_1;
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/* [0xc] Reserved for future use */
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uint32_t general_cfg_2;
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/* [0x10] Reserved for future use */
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uint32_t general_cfg_3;
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/* [0x14] Reserved for future use */
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uint32_t general_cfg_4;
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/* [0x18] General timer configuration */
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uint32_t general_cfg_5;
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uint32_t rsrvd[57];
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};
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struct udma_gen_mailbox {
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/*
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* [0x0] Mailbox interrupt generator.
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* Generates interrupt to neighbor DMA
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*/
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uint32_t interrupt;
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/* [0x4] Mailbox message data out */
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uint32_t msg_out;
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/* [0x8] Mailbox message data in */
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uint32_t msg_in;
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uint32_t rsrvd[13];
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};
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struct udma_gen_axi {
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/* [0x0] Configuration of the AXI masters */
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uint32_t cfg_1;
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/* [0x4] Configuration of the AXI masters */
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uint32_t cfg_2;
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/* [0x8] Configuration of the AXI masters. Endianess configuration */
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uint32_t endian_cfg;
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uint32_t rsrvd[61];
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};
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struct udma_gen_sram_ctrl {
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/* [0x0] Timing configuration */
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uint32_t timing;
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};
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struct udma_gen_tgtid {
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/* [0x0] Target-ID control */
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uint32_t cfg_tgtid_0;
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/* [0x4] TX queue 0/1 Target-ID */
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uint32_t cfg_tgtid_1;
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/* [0x8] TX queue 2/3 Target-ID */
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uint32_t cfg_tgtid_2;
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/* [0xc] RX queue 0/1 Target-ID */
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uint32_t cfg_tgtid_3;
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/* [0x10] RX queue 2/3 Target-ID */
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uint32_t cfg_tgtid_4;
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};
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struct udma_gen_tgtaddr {
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/* [0x0] TX queue 0/1 Target-Address */
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uint32_t cfg_tgtaddr_0;
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/* [0x4] TX queue 2/3 Target-Address */
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uint32_t cfg_tgtaddr_1;
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/* [0x8] RX queue 0/1 Target-Address */
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uint32_t cfg_tgtaddr_2;
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/* [0xc] RX queue 2/3 Target-Address */
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uint32_t cfg_tgtaddr_3;
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};
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struct udma_gen_vmpr {
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/* [0x0] TX VMPR control */
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uint32_t cfg_vmpr_0;
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/* [0x4] TX VMPR Address High Regsiter */
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uint32_t cfg_vmpr_1;
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/* [0x8] TX queue Target-ID values */
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uint32_t cfg_vmpr_2;
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/* [0xc] TX queue Target-ID values */
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uint32_t cfg_vmpr_3;
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/* [0x10] RX VMPR control */
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uint32_t cfg_vmpr_4;
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/* [0x14] RX VMPR Buffer2 MSB address */
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uint32_t cfg_vmpr_5;
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/* [0x18] RX queue Target-ID values */
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uint32_t cfg_vmpr_6;
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/* [0x1c] RX queue BUF1 Target-ID values */
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uint32_t cfg_vmpr_7;
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/* [0x20] RX queue BUF2 Target-ID values */
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uint32_t cfg_vmpr_8;
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/* [0x24] RX queue Direct Data Placement Target-ID values */
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uint32_t cfg_vmpr_9;
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/* [0x28] RX VMPR BUF1 Address High Regsiter */
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uint32_t cfg_vmpr_10;
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/* [0x2c] RX VMPR BUF2 Address High Regsiter */
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uint32_t cfg_vmpr_11;
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/* [0x30] RX VMPR DDP Address High Regsiter */
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uint32_t cfg_vmpr_12;
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uint32_t rsrvd[3];
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};
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struct udma_gen_regs {
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struct udma_iofic_regs interrupt_regs; /* [0x0000] */
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struct udma_gen_dma_misc dma_misc; /* [0x2080] */
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struct udma_gen_mailbox mailbox[4]; /* [0x2180] */
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struct udma_gen_axi axi; /* [0x2280] */
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struct udma_gen_sram_ctrl sram_ctrl[25]; /* [0x2380] */
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uint32_t rsrvd_1[2];
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struct udma_gen_tgtid tgtid; /* [0x23ec] */
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struct udma_gen_tgtaddr tgtaddr; /* [0x2400] */
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uint32_t rsrvd_2[252];
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struct udma_gen_vmpr vmpr[4]; /* [0x2800] */
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};
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/*
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* Registers Fields
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*/
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/**** int_cfg register ****/
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/*
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* MSIX data width
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* 1 - 64 bit
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* 0 – 32 bit
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*/
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#define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_64 (1 << 0)
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/* General configuration */
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#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_3_1_MASK 0x0000000E
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#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_3_1_SHIFT 1
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/* MSIx AXI QoS */
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#define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_AXI_QOS_MASK 0x00000070
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#define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_AXI_QOS_SHIFT 4
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#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_31_7_MASK 0xFFFFFF80
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#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_31_7_SHIFT 7
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/**** revision register ****/
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/* Design programming interface revision ID */
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#define UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_MASK 0x00000FFF
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#define UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_SHIFT 0
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/* Design minor revision ID */
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#define UDMA_GEN_DMA_MISC_REVISION_MINOR_ID_MASK 0x00FFF000
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#define UDMA_GEN_DMA_MISC_REVISION_MINOR_ID_SHIFT 12
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/* Design major revision ID */
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#define UDMA_GEN_DMA_MISC_REVISION_MAJOR_ID_MASK 0xFF000000
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#define UDMA_GEN_DMA_MISC_REVISION_MAJOR_ID_SHIFT 24
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/**** Interrupt register ****/
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/* Generate interrupt to another DMA */
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#define UDMA_GEN_MAILBOX_INTERRUPT_SET (1 << 0)
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/**** cfg_2 register ****/
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/*
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* Enable arbitration promotion.
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* Increment master priority after configured number of arbitration cycles
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*/
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#define UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_MASK 0x0000000F
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#define UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_SHIFT 0
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/**** endian_cfg register ****/
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/* Swap M2S descriptor read and completion descriptor write. */
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#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC (1 << 0)
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/* Swap M2S data read. */
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#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DATA (1 << 1)
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/* Swap S2M descriptor read and completion descriptor write. */
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#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DESC (1 << 2)
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/* Swap S2M data write. */
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#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA (1 << 3)
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/*
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* Swap 32 or 64 bit mode:
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* 0 - Swap groups of 4 bytes
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* 1 - Swap groups of 8 bytes
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*/
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#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN (1 << 4)
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/**** timing register ****/
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/* Write margin */
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#define UDMA_GEN_SRAM_CTRL_TIMING_RMA_MASK 0x0000000F
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#define UDMA_GEN_SRAM_CTRL_TIMING_RMA_SHIFT 0
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/* Write margin enable */
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#define UDMA_GEN_SRAM_CTRL_TIMING_RMEA (1 << 8)
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/* Read margin */
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#define UDMA_GEN_SRAM_CTRL_TIMING_RMB_MASK 0x000F0000
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#define UDMA_GEN_SRAM_CTRL_TIMING_RMB_SHIFT 16
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/* Read margin enable */
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#define UDMA_GEN_SRAM_CTRL_TIMING_RMEB (1 << 24)
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/**** cfg_tgtid_0 register ****/
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/* For M2S queues 3:0, enable usage of the Target-ID from the buffer address 63:56 */
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#define UDMA_GEN_TGTID_CFG_TGTID_0_TX_Q_TGTID_DESC_EN_MASK 0x0000000F
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#define UDMA_GEN_TGTID_CFG_TGTID_0_TX_Q_TGTID_DESC_EN_SHIFT 0
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/*
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* For M2S queues 3:0, enable usage of the Target-ID from the configuration register
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* (cfg_tgtid_1/2 used for M2S queue_x)
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*/
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#define UDMA_GEN_TGTID_CFG_TGTID_0_TX_Q_TGTID_QUEUE_EN_MASK 0x000000F0
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#define UDMA_GEN_TGTID_CFG_TGTID_0_TX_Q_TGTID_QUEUE_EN_SHIFT 4
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/* use Target-ID_n [7:0] from MSI-X Controller for MSI-X message */
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#define UDMA_GEN_TGTID_CFG_TGTID_0_MSIX_TGTID_SEL (1 << 8)
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/* Enable write to all Target-ID_n registers in the MSI-X Controller */
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#define UDMA_GEN_TGTID_CFG_TGTID_0_MSIX_TGTID_ACCESS_EN (1 << 9)
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/* For S2M queues 3:0, enable usage of the Target-ID from the buffer address 63:56 */
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#define UDMA_GEN_TGTID_CFG_TGTID_0_RX_Q_TGTID_DESC_EN_MASK 0x000F0000
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#define UDMA_GEN_TGTID_CFG_TGTID_0_RX_Q_TGTID_DESC_EN_SHIFT 16
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/*
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* For S2M queues 3:0, enable usage of the Target-ID from the configuration register
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* (cfg_tgtid_3/4 used for M2S queue_x)
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*/
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#define UDMA_GEN_TGTID_CFG_TGTID_0_RX_Q_TGTID_QUEUE_EN_MASK 0x00F00000
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#define UDMA_GEN_TGTID_CFG_TGTID_0_RX_Q_TGTID_QUEUE_EN_SHIFT 20
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#define UDMA_GEN_TGTID_CFG_TGTID_SHIFT(qid) (((qid) & 0x1) ? 16 : 0)
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#define UDMA_GEN_TGTID_CFG_TGTID_MASK(qid) (((qid) & 0x1) ? 0xFFFF0000 : 0x0000FFFF)
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/**** cfg_tgtid_1 register ****/
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/* TX queue 0 Target-ID value */
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#define UDMA_GEN_TGTID_CFG_TGTID_1_TX_Q_0_TGTID_MASK 0x0000FFFF
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#define UDMA_GEN_TGTID_CFG_TGTID_1_TX_Q_0_TGTID_SHIFT 0
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/* TX queue 1 Target-ID value */
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#define UDMA_GEN_TGTID_CFG_TGTID_1_TX_Q_1_TGTID_MASK 0xFFFF0000
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#define UDMA_GEN_TGTID_CFG_TGTID_1_TX_Q_1_TGTID_SHIFT 16
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/**** cfg_tgtid_2 register ****/
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/* TX queue 2 Target-ID value */
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#define UDMA_GEN_TGTID_CFG_TGTID_2_TX_Q_2_TGTID_MASK 0x0000FFFF
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#define UDMA_GEN_TGTID_CFG_TGTID_2_TX_Q_2_TGTID_SHIFT 0
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/* TX queue 3 Target-ID value */
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#define UDMA_GEN_TGTID_CFG_TGTID_2_TX_Q_3_TGTID_MASK 0xFFFF0000
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#define UDMA_GEN_TGTID_CFG_TGTID_2_TX_Q_3_TGTID_SHIFT 16
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/**** cfg_tgtid_3 register ****/
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/* RX queue 0 Target-ID value */
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#define UDMA_GEN_TGTID_CFG_TGTID_3_RX_Q_0_TGTID_MASK 0x0000FFFF
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#define UDMA_GEN_TGTID_CFG_TGTID_3_RX_Q_0_TGTID_SHIFT 0
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/* RX queue 1 Target-ID value */
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#define UDMA_GEN_TGTID_CFG_TGTID_3_RX_Q_1_TGTID_MASK 0xFFFF0000
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#define UDMA_GEN_TGTID_CFG_TGTID_3_RX_Q_1_TGTID_SHIFT 16
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/**** cfg_tgtid_4 register ****/
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/* RX queue 2 Target-ID value */
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#define UDMA_GEN_TGTID_CFG_TGTID_4_RX_Q_2_TGTID_MASK 0x0000FFFF
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#define UDMA_GEN_TGTID_CFG_TGTID_4_RX_Q_2_TGTID_SHIFT 0
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/* RX queue 3 Target-ID value */
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#define UDMA_GEN_TGTID_CFG_TGTID_4_RX_Q_3_TGTID_MASK 0xFFFF0000
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#define UDMA_GEN_TGTID_CFG_TGTID_4_RX_Q_3_TGTID_SHIFT 16
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#define UDMA_GEN_TGTADDR_CFG_SHIFT(qid) (((qid) & 0x1) ? 16 : 0)
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#define UDMA_GEN_TGTADDR_CFG_MASK(qid) (((qid) & 0x1) ? 0xFFFF0000 : 0x0000FFFF)
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/**** cfg_tgtaddr_0 register ****/
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/* TX queue 0 Target-Address value */
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_0_TX_Q_0_TGTADDR_MASK 0x0000FFFF
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_0_TX_Q_0_TGTADDR_SHIFT 0
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/* TX queue 1 Target-Address value */
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_0_TX_Q_1_TGTADDR_MASK 0xFFFF0000
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_0_TX_Q_1_TGTADDR_SHIFT 16
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/**** cfg_tgtaddr_1 register ****/
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/* TX queue 2 Target-Address value */
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_1_TX_Q_2_TGTADDR_MASK 0x0000FFFF
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_1_TX_Q_2_TGTADDR_SHIFT 0
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/* TX queue 3 Target-Address value */
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_1_TX_Q_3_TGTADDR_MASK 0xFFFF0000
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_1_TX_Q_3_TGTADDR_SHIFT 16
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/**** cfg_tgtaddr_2 register ****/
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/* RX queue 0 Target-Address value */
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_2_RX_Q_0_TGTADDR_MASK 0x0000FFFF
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_2_RX_Q_0_TGTADDR_SHIFT 0
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/* RX queue 1 Target-Address value */
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_2_RX_Q_1_TGTADDR_MASK 0xFFFF0000
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_2_RX_Q_1_TGTADDR_SHIFT 16
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/**** cfg_tgtaddr_3 register ****/
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/* RX queue 2 Target-Address value */
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_3_RX_Q_2_TGTADDR_MASK 0x0000FFFF
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_3_RX_Q_2_TGTADDR_SHIFT 0
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/* RX queue 3 Target-Address value */
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_3_RX_Q_3_TGTADDR_MASK 0xFFFF0000
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#define UDMA_GEN_TGTADDR_CFG_TGTADDR_3_RX_Q_3_TGTADDR_SHIFT 16
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/**** cfg_vmpr_0 register ****/
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/* TX High Address Select Per Q */
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#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_MASK 0x0000003F
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#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_SHIFT 0
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/* TX Data Target-ID Enable Per Q */
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#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_DATA_TGTID_EN (1 << 7)
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/* TX Prefetch Target-ID Enable Per Q */
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#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_PREF_TGTID_EN (1 << 28)
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/* TX Completions Target-ID Enable Per Q */
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#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_CMPL_TGTID_EN (1 << 29)
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/**** cfg_vmpr_2 register ****/
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/* TX queue Prefetch Target-ID */
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#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_TGTID_MASK 0x0000FFFF
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#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_TGTID_SHIFT 0
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/* TX queue Completion Target-ID */
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#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_TGTID_MASK 0xFFFF0000
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#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_TGTID_SHIFT 16
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/**** cfg_vmpr_3 register ****/
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/* TX queue Data Target-ID */
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#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_TGTID_MASK 0x0000FFFF
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#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_TGTID_SHIFT 0
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/* TX queue Data Target-ID select */
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#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_TGTID_SEL_MASK 0xFFFF0000
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#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_TGTID_SEL_SHIFT 16
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/**** cfg_vmpr_4 register ****/
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/* RX Data Buffer1 - High Address Select Per Q */
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#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_MASK 0x0000003F
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#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_SHIFT 0
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/* RX Data Buffer1 Target-ID Enable Per Q */
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#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_TGTID_EN (1 << 7)
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/* RX Data Buffer2 - High Address Select Per Q */
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#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_MASK 0x00003F00
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#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_SHIFT 8
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/* RX Data Buffer2 Target-ID Enable Per Q */
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#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_TGTID_EN (1 << 15)
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/* RX Direct Data Placement - High Address Select Per Q */
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#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_MASK 0x003F0000
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#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_SHIFT 16
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/* RX Direct Data Placement Target-ID Enable Per Q */
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#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_TGTID_EN (1 << 23)
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/* RX Buffer 2 MSB address word selects per bytes, per queue */
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#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_MASK 0x0F000000
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#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_SHIFT 24
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/* RX Prefetch Target-ID Enable Per Q */
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#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_PREF_TGTID_EN (1 << 28)
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/* RX Completions Target-ID Enable Per Q */
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#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_CMPL_TGTID_EN (1 << 29)
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/**** cfg_vmpr_6 register ****/
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/* RX queue Prefetch Target-ID */
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#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_TGTID_MASK 0x0000FFFF
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#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_TGTID_SHIFT 0
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/* RX queue Completion Target-ID */
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#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_TGTID_MASK 0xFFFF0000
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#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_TGTID_SHIFT 16
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/**** cfg_vmpr_7 register ****/
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/* RX queue Data Buffer 1 Target-ID */
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#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_TGTID_MASK 0x0000FFFF
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#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_TGTID_SHIFT 0
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/* RX queue Data Buffer 1 Target-ID select */
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#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_TGTID_SEL_MASK 0xFFFF0000
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#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_TGTID_SEL_SHIFT 16
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/**** cfg_vmpr_8 register ****/
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/* RX queue Data Buffer 2 Target-ID */
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#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_TGTID_MASK 0x0000FFFF
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#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_TGTID_SHIFT 0
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/* RX queue Data Buffer 2 Target-ID select */
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#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_TGTID_SEL_MASK 0xFFFF0000
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#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_TGTID_SEL_SHIFT 16
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/**** cfg_vmpr_9 register ****/
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/* RX queue DDP Target-ID */
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#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_TGTID_MASK 0x0000FFFF
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#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_TGTID_SHIFT 0
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/* RX queue DDP Target-ID select */
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#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_TGTID_SEL_MASK 0xFFFF0000
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#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_TGTID_SEL_SHIFT 16
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#ifdef __cplusplus
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}
|
||
#endif
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#endif /* __AL_HAL_UDMA_GEN_REG_H */
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