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106 lines
3.3 KiB
C
106 lines
3.3 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2008 Nathan Whitehorn
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _POWERPC_POWERMAC_DBDMAVAR_H_
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#define _POWERPC_POWERMAC_DBDMAVAR_H_
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struct dbdma_command {
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uint8_t cmd:4; /* DBDMA command */
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uint8_t _resd1:1;
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uint8_t key:3; /* Stream number, or 6 for KEY_SYSTEM */
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uint8_t _resd2:2;
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/* Interrupt, branch, and wait flags */
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uint8_t intr:2;
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uint8_t branch:2;
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uint8_t wait:2;
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uint16_t reqCount; /* Bytes to transfer */
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uint32_t address; /* 32-bit system physical address */
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uint32_t cmdDep; /* Branch address or quad word to load/store */
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uint16_t xferStatus; /* Contents of channel status after completion */
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uint16_t resCount; /* Number of residual bytes outstanding */
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};
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struct dbdma_channel {
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struct resource *sc_regs;
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u_int sc_off;
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struct dbdma_command *sc_slots;
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int sc_nslots;
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bus_addr_t sc_slots_pa;
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bus_dma_tag_t sc_dmatag;
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bus_dmamap_t sc_dmamap;
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uint32_t sc_saved_regs[5];
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};
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/*
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DBDMA registers are found at 0x8000 + n*0x100 in the macio register space,
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and are laid out as follows within each block:
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Address: Description: Length (bytes):
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0x000 Channel Control 4
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0x004 Channel Status 4
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0x00C Command Phys Addr 4
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0x010 Interrupt Select 4
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0x014 Branch Select 4
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0x018 Wait Select 4
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*/
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#define CHAN_CONTROL_REG 0x00
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#define CHAN_STATUS_REG 0x04
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#define CHAN_CMDPTR_HI 0x08
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#define CHAN_CMDPTR 0x0C
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#define CHAN_INTR_SELECT 0x10
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#define CHAN_BRANCH_SELECT 0x14
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#define CHAN_WAIT_SELECT 0x18
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/* Channel control is the write channel to channel status, the upper 16 bits
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are a mask of which bytes to change */
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#define DBDMA_REG_MASK_SHIFT 16
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/* Status bits 0-7 are device dependent status bits */
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/*
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The Interrupt/Branch/Wait Select triggers the corresponding condition bits
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in the event that (select.mask & device dependent status) == select.value
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They are defined a follows:
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Byte 1: Reserved
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Byte 2: Mask
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Byte 3: Reserved
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Byte 4: Value
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*/
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#endif /* _POWERPC_POWERMAC_DBDMAVAR_H_ */
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