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a9b9e46550
and initializes the next two ports in order starting at 03e0. This also patches pcic_p.h to reduce the I/O ports mapped from 4 to 2. Submitted by: Ted Faber <faber@ISI.EDU>
55 lines
2.3 KiB
C
55 lines
2.3 KiB
C
/*
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* Copyright (c) 1997 Ted Faber
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Absolutely no warranty of function or purpose is made by the author
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* Ted Faber.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: pcic_p.h,v 1.2 1997/12/02 22:13:59 nate Exp $
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*/
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/* PCI/CardBus Device IDs */
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#define PCI_DEVICE_ID_PCIC_CLPD6729 0x11001013ul
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#define PCI_DEVICE_ID_PCIC_CLPD6832 0x11101013ul
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#define PCI_DEVICE_ID_PCIC_O2MICRO 0x673A1217ul
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#define PCI_DEVICE_ID_PCIC_TI1130 0xAC12104Cul
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#define PCI_DEVICE_ID_PCIC_TI1131 0xAC15104Cul
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/* CL-PD6832 CardBus defines */
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#define CLPD6832_IO_BASE0 0x002c
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#define CLPD6832_IO_LIMIT0 0x0030
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#define CLPD6832_IO_BASE1 0x0034
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#define CLPD6832_IO_LIMIT1 0x0038
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#define CLPD6832_BRIDGE_CONTROL 0x003c
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#define CLPD6832_LEGACY_16BIT_IOADDR 0x0044
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#define CLPD6832_SOCKET 0x004c
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/* Configuration constants */
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#define CLPD6832_BCR_MGMT_IRQ_ENA 0x08000000
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#define CLPD6832_BCR_ISA_IRQ 0x00800000
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#define CLPD6832_COMMAND_DEFAULTS 0x00000045
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#define CLPD6832_NUM_REGS 2
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/* End of CL-PD6832 defines */
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