2023-09-28 20:40:55 +02:00
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/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __DWC1000_DMA_H__
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#define __DWC1000_DMA_H__
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/*
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* A hardware buffer descriptor. Rx and Tx buffers have the same descriptor
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* layout, but the bits in the fields have different meanings.
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*/
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struct dwc_hwdesc
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{
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uint32_t desc0;
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uint32_t desc1;
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uint32_t addr1; /* ptr to first buffer data */
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uint32_t addr2; /* ptr to next descriptor / second buffer data*/
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};
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int dma1000_init(struct dwc_softc *sc);
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void dma1000_free(struct dwc_softc *sc);
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void dma1000_start(struct dwc_softc *sc);
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void dma1000_stop(struct dwc_softc *sc);
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int dma1000_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp);
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void dma1000_txfinish_locked(struct dwc_softc *sc);
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void dma1000_rxfinish_locked(struct dwc_softc *sc);
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2023-09-28 22:34:47 +02:00
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void dma1000_txstart(struct dwc_softc *sc);
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2023-10-03 18:04:03 +02:00
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int dma1000_intr(struct dwc_softc *sc);
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2023-09-28 20:40:55 +02:00
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#endif /* __DWC1000_DMA_H__ */
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