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dwc: Setup desc addresses in the dma init function.
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29776aa436
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f0a7dd7703
@ -605,10 +605,18 @@ int
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dma1000_init(struct dwc_softc *sc)
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{
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struct mbuf *m;
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uint32_t reg;
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int error;
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int nidx;
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int idx;
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/*
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* DMA must be stop while changing descriptor list addresses.
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*/
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reg = READ4(sc, OPERATION_MODE);
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reg &= ~(MODE_ST | MODE_SR);
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WRITE4(sc, OPERATION_MODE, reg);
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/*
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* Set up TX descriptor ring, descriptors, and dma maps.
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*/
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@ -684,6 +692,8 @@ dma1000_init(struct dwc_softc *sc)
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for (idx = 0; idx < TX_DESC_COUNT; idx++)
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dwc_setup_txdesc(sc, idx, 0, 0, 0, false, false);
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WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr);
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/*
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* Set up RX descriptor ring, descriptors, dma maps, and mbufs.
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*/
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@ -758,6 +768,7 @@ dma1000_init(struct dwc_softc *sc)
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goto out;
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}
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}
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WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr);
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out:
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if (error != 0)
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@ -610,22 +610,11 @@ dwc_attach(device_t dev)
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WRITE4(sc, BUS_MODE, reg);
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/*
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* DMA must be stop while changing descriptor list addresses.
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*/
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reg = READ4(sc, OPERATION_MODE);
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reg &= ~(MODE_ST | MODE_SR);
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WRITE4(sc, OPERATION_MODE, reg);
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if (dma1000_init(sc)) {
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bus_release_resources(dev, dwc_spec, sc->res);
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return (ENXIO);
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}
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/* Setup addresses */
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WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr);
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WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr);
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mtx_init(&sc->mtx, device_get_nameunit(sc->dev),
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MTX_NETWORK_LOCK, MTX_DEF);
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