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https://git.hardenedbsd.org/hardenedbsd/HardenedBSD.git
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c3c50c4e3a
Further experimentation showed that some Dell 2450 machines with the prevention kludge installed still got T_RESERVED traps. CPU interrupt vector 0x7A was observed to be triggered. This might have been the bitwise OR of two different vectors sent from each of the IOAPICs at the same time. IOAPIC #0: 0x68 --> irq 8: RTC timer interrupt IOAPIC #1: 0x32 --> irq 18: scsi host adapter or network interface ---- 0x7a --> T_RESERVED Both IOAPICs had ID 0. Appendix B.3 in the MP spec indicates that the operating system is responsible for assigning unique IDs to the IOAPICs. The enclosed patch programs the IOAPIC IDs according to the IOAPIC entries in the MP table. Submitted by: tegge
207 lines
5.4 KiB
C
207 lines
5.4 KiB
C
/*
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* ----------------------------------------------------------------------------
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* "THE BEER-WARE LICENSE" (Revision 42):
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* <phk@FreeBSD.org> wrote this file. As long as you retain this notice you
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* can do whatever you want with this stuff. If we meet some day, and you think
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* this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
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* ----------------------------------------------------------------------------
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*
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* $FreeBSD$
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*
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*/
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#ifndef _MACHINE_SMP_H_
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#define _MACHINE_SMP_H_
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#ifdef _KERNEL
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#if defined(SMP) && !defined(APIC_IO)
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# error APIC_IO required for SMP, add "options APIC_IO" to your config file.
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#endif /* SMP && !APIC_IO */
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/* Number of CPUs. */
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#if defined(SMP) && !defined(NCPU)
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# define NCPU 2
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#endif /* SMP && NCPU */
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/* Number of IO APICs. */
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#if defined(APIC_IO) && !defined(NAPIC)
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# define NAPIC 1
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#endif /* SMP && NAPIC */
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#if defined(SMP) || defined(APIC_IO)
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#ifndef LOCORE
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/*
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* For sending values to POST displays.
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* XXX FIXME: where does this really belong, isa.h/isa.c perhaps?
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*/
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extern int current_postcode; /** XXX currently in mp_machdep.c */
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#define POSTCODE(X) current_postcode = (X), \
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outb(0x80, current_postcode)
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#define POSTCODE_LO(X) current_postcode &= 0xf0, \
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current_postcode |= ((X) & 0x0f), \
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outb(0x80, current_postcode)
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#define POSTCODE_HI(X) current_postcode &= 0x0f, \
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current_postcode |= (((X) << 4) & 0xf0), \
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outb(0x80, current_postcode)
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#include <machine/apic.h>
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/* global data in mpboot.s */
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extern int bootMP_size;
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/* functions in mpboot.s */
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void bootMP __P((void));
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/* global data in mplock.s */
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extern u_int mp_lock;
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extern u_int isr_lock;
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#ifdef RECURSIVE_MPINTRLOCK
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extern u_int mpintr_lock;
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#endif /* RECURSIVE_MPINTRLOCK */
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/* functions in mplock.s */
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void get_mplock __P((void));
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void rel_mplock __P((void));
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int try_mplock __P((void));
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#ifdef RECURSIVE_MPINTRLOCK
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void get_mpintrlock __P((void));
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void rel_mpintrlock __P((void));
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int try_mpintrlock __P((void));
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#endif /* RECURSIVE_MPINTRLOCK */
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/* global data in apic_vector.s */
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extern volatile u_int stopped_cpus;
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extern volatile u_int started_cpus;
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extern volatile u_int checkstate_probed_cpus;
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extern volatile u_int checkstate_need_ast;
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extern volatile u_int resched_cpus;
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extern void (*cpustop_restartfunc) __P((void));
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/* functions in apic_ipl.s */
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void apic_eoi __P((void));
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u_int io_apic_read __P((int, int));
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void io_apic_write __P((int, int, u_int));
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/* global data in mp_machdep.c */
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extern int bsp_apic_ready;
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extern int mp_ncpus;
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extern int mp_naps;
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extern int mp_nbusses;
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extern int mp_napics;
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extern int mp_picmode;
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extern int boot_cpu_id;
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extern vm_offset_t cpu_apic_address;
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extern vm_offset_t io_apic_address[];
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extern u_int32_t cpu_apic_versions[];
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extern u_int32_t io_apic_versions[];
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extern int cpu_num_to_apic_id[];
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extern int io_num_to_apic_id[];
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extern int apic_id_to_logical[];
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#define APIC_INTMAPSIZE 24
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struct apic_intmapinfo {
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int ioapic;
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int int_pin;
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volatile void *apic_address;
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int redirindex;
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};
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extern struct apic_intmapinfo int_to_apicintpin[];
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extern u_int all_cpus;
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extern struct pcb stoppcbs[];
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/* functions in mp_machdep.c */
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u_int mp_bootaddress __P((u_int));
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int mp_probe __P((void));
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void mp_start __P((void));
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void mp_announce __P((void));
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u_int isa_apic_mask __P((u_int));
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int isa_apic_irq __P((int));
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int pci_apic_irq __P((int, int, int));
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int apic_irq __P((int, int));
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int next_apic_irq __P((int));
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int undirect_isa_irq __P((int));
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int undirect_pci_irq __P((int));
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int apic_bus_type __P((int));
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int apic_src_bus_id __P((int, int));
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int apic_src_bus_irq __P((int, int));
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int apic_int_type __P((int, int));
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int apic_trigger __P((int, int));
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int apic_polarity __P((int, int));
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void assign_apic_irq __P((int apic, int intpin, int irq));
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void revoke_apic_irq __P((int irq));
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void bsp_apic_configure __P((void));
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void init_secondary __P((void));
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void smp_invltlb __P((void));
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int stop_cpus __P((u_int));
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int restart_cpus __P((u_int));
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#ifdef BETTER_CLOCK
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void forward_statclock __P((int pscnt));
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void forward_hardclock __P((int pscnt));
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#endif /* BETTER_CLOCK */
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void forward_signal __P((struct proc *));
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void forward_roundrobin __P((void));
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#ifdef APIC_INTR_REORDER
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void set_lapic_isrloc __P((int, int));
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#endif /* APIC_INTR_REORDER */
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void smp_rendezvous_action __P((void));
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void smp_rendezvous __P((void (*)(void *),
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void (*)(void *),
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void (*)(void *),
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void *arg));
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/* global data in mpapic.c */
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extern volatile lapic_t lapic;
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extern volatile ioapic_t *ioapic[];
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/* functions in mpapic.c */
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void apic_dump __P((char*));
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void apic_initialize __P((void));
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void imen_dump __P((void));
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int apic_ipi __P((int, int, int));
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int selected_apic_ipi __P((u_int, int, int));
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int io_apic_setup __P((int));
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void io_apic_set_id __P((int, int));
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int ext_int_setup __P((int, int));
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#if defined(READY)
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void clr_io_apic_mask24 __P((int, u_int32_t));
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void set_io_apic_mask24 __P((int, u_int32_t));
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#endif /* READY */
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void set_apic_timer __P((int));
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int read_apic_timer __P((void));
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void u_sleep __P((int));
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/* global data in init_smp.c */
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extern int invltlb_ok;
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extern int smp_active;
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extern int smp_started;
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extern volatile int smp_idle_loops;
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#endif /* !LOCORE */
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#else /* !SMP && !APIC_IO */
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/*
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* Create dummy MP lock empties
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*/
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static __inline void
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get_mplock(void)
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{
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}
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static __inline void
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rel_mplock(void)
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{
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}
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#endif
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#endif /* _KERNEL */
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#endif /* _MACHINE_SMP_H_ */
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