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435 lines
14 KiB
C
435 lines
14 KiB
C
/*******************************************************************************
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Copyright (C) 2013 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 or V3 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/**
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* @{
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* @file al_hal_serdes_c_regs.h
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*
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* @brief ... registers
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*
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*/
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#ifndef __AL_HAL_serdes_c_REGS_H__
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#define __AL_HAL_serdes_c_REGS_H__
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#include "al_hal_plat_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Unit Registers
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*/
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struct al_serdes_c_gen {
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/* [0x0] SERDES registers Version */
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uint32_t version;
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uint32_t rsrvd_0[3];
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/* [0x10] SERDES register file address */
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uint32_t reg_addr;
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/* [0x14] SERDES register file data */
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uint32_t reg_data;
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/* [0x18] SERDES control */
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uint32_t ctrl;
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/* [0x1c] SERDES cpu mem address */
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uint32_t cpu_prog_addr;
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/* [0x20] SERDES cpu mem data */
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uint32_t cpu_prog_data;
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/* [0x24] SERDES data mem address */
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uint32_t cpu_data_mem_addr;
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/* [0x28] SERDES data mem data */
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uint32_t cpu_data_mem_data;
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/* [0x2c] SERDES control */
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uint32_t rst;
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/* [0x30] SERDES control */
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uint32_t status;
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uint32_t rsrvd[51];
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};
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struct al_serdes_c_lane {
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uint32_t rsrvd_0[4];
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/* [0x10] Data configuration */
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uint32_t cfg;
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/* [0x14] Lane status */
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uint32_t stat;
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/* [0x18] SERDES control */
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uint32_t reserved;
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uint32_t rsrvd[25];
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};
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struct al_serdes_c_regs {
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uint32_t rsrvd_0[64];
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struct al_serdes_c_gen gen; /* [0x100] */
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struct al_serdes_c_lane lane[2]; /* [0x200] */
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};
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/*
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* Registers Fields
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*/
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/**** version register ****/
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/* Revision number (Minor) */
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#define SERDES_C_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
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#define SERDES_C_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
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/* Revision number (Major) */
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#define SERDES_C_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
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#define SERDES_C_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
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/* date of release */
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#define SERDES_C_GEN_VERSION_DATE_DAY_MASK 0x001F0000
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#define SERDES_C_GEN_VERSION_DATE_DAY_SHIFT 16
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/* month of release */
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#define SERDES_C_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
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#define SERDES_C_GEN_VERSION_DATA_MONTH_SHIFT 21
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/* year of release (starting from 2000) */
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#define SERDES_C_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
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#define SERDES_C_GEN_VERSION_DATE_YEAR_SHIFT 25
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/* Reserved */
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#define SERDES_C_GEN_VERSION_RESERVED_MASK 0xC0000000
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#define SERDES_C_GEN_VERSION_RESERVED_SHIFT 30
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/**** reg_addr register ****/
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/* address value */
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#define SERDES_C_GEN_REG_ADDR_VAL_MASK 0x00007FFF
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#define SERDES_C_GEN_REG_ADDR_VAL_SHIFT 0
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/**** reg_data register ****/
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/* data value */
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#define SERDES_C_GEN_REG_DATA_VAL_MASK 0x000000FF
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#define SERDES_C_GEN_REG_DATA_VAL_SHIFT 0
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/* Bit-wise write enable */
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#define SERDES_C_GEN_REG_DATA_STRB_MASK 0x0000FF00
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#define SERDES_C_GEN_REG_DATA_STRB_SHIFT 8
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/**** ctrl register ****/
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/*
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* 0x0 – Select reference clock from Bump
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* 0x1 – Select inter-macro reference clock from the left side
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* 0x2 – Same as 0x0
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* 0x3 – Select inter-macro reference clock from the right side
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*/
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#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_MASK 0x00000003
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#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT 0
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#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_REF \
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(0 << (SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT))
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#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_L2R \
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(1 << (SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT))
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#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_R2L \
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(3 << (SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT))
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/*
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* 0x0 – Tied to 0 to save power
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* 0x1 – Select reference clock from Bump
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* 0x2 – Select inter-macro reference clock input from right side
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* 0x3 – Same as 0x2
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*/
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#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_MASK 0x00000030
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#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT 4
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#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_0 \
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(0 << (SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT))
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#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_REF \
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(1 << (SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT))
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#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_R2L \
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(2 << (SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT))
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/*
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* 0x0 – Tied to 0 to save power
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* 0x1 – Select reference clock from Bump
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* 0x2 – Select inter-macro reference clock input from left side
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* 0x3 – Same as 0x2
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*/
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#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_MASK 0x000000C0
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#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT 6
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#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_0 \
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(0 << (SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT))
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#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_REF \
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(1 << (SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT))
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#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_L2R \
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(2 << (SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT))
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/*
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* Program memory acknowledge - Only when the access
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* to the program memory is not
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* ready for the microcontroller, it
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* is driven to 0
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*/
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#define SERDES_C_GEN_CTRL_CPU_MEMPSACK (1 << 8)
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/*
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* Data memory acknowledge - Only when the access
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* to the program memory is not
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* ready for the microcontroller, it
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* is driven to 0
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*/
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#define SERDES_C_GEN_CTRL_CPU_MEMACK (1 << 12)
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/*
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* 0 - keep cpu clk as sb clk
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* 1 – cpu_clk is sb_clk divided by 2
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*/
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#define SERDES_C_GEN_CTRL_CPU_CLK_DIV (1 << 16)
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/*
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* 0x0 – OIF CEI-28G-SR
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* 0x1 – OIF CIE-25G-LR
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* 0x8 – XFI
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* Others – Reserved
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*
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* Note that phy_ctrl_cfg_i[3] is used to signify high-speed/low-speed
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*/
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#define SERDES_C_GEN_CTRL_PHY_CTRL_CFG_MASK 0x00F00000
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#define SERDES_C_GEN_CTRL_PHY_CTRL_CFG_SHIFT 20
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/*
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* 0 - Internal 8051 micro- controller is allowed to access the internal APB
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* CSR. Internal APB runs at cpu_clk_i, and the accesses from the external APB
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* in apb_clk_i domain to APB CSR are resynchronized to cpu_clk_i. 1 – Bypass
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* CPU. Internal 8051 micro-controller is blocked from accessing the internal
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* APB CSR. Internal APB runs at apb_clk_i.
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*/
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#define SERDES_C_GEN_CTRL_CPU_BYPASS (1 << 24)
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/**** cpu_prog_addr register ****/
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/*
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* address value 32 bit,
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* The firmware data will be 1 byte with 64K rows
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*/
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#define SERDES_C_GEN_CPU_PROG_ADDR_VAL_MASK 0x00007FFF
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#define SERDES_C_GEN_CPU_PROG_ADDR_VAL_SHIFT 0
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/**** cpu_data_mem_addr register ****/
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/* address value – 8K byte memory */
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#define SERDES_C_GEN_CPU_DATA_MEM_ADDR_VAL_MASK 0x00001FFF
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#define SERDES_C_GEN_CPU_DATA_MEM_ADDR_VAL_SHIFT 0
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/**** cpu_data_mem_data register ****/
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/* data value */
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#define SERDES_C_GEN_CPU_DATA_MEM_DATA_VAL_MASK 0x000000FF
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#define SERDES_C_GEN_CPU_DATA_MEM_DATA_VAL_SHIFT 0
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/**** rst register ****/
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/* Power on reset Signal – active low */
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#define SERDES_C_GEN_RST_POR_N (1 << 0)
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/* CMU reset Active low */
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#define SERDES_C_GEN_RST_CM0_RST_N (1 << 1)
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/*
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* 0x0 – Normal / Active
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* 0x1 – Partial power down
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* 0x2 – Near complete power down (only
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* refclk buffers and portions of analog bias
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* active)
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* 0x3 – complete power down (IDDQ mode)
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* Can be asserted when CMU is in normal
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* mode. These modes provide an increased
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* power savings compared to reset mode.
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* Signal is overridden by por_n_i so has no
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* effect in power on reset state.
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*/
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#define SERDES_C_GEN_RST_CM0_PD_MASK 0x00000030
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#define SERDES_C_GEN_RST_CM0_PD_SHIFT 4
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/* Lane0 reset signal active low */
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#define SERDES_C_GEN_RST_LN0_RST_N (1 << 6)
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/* Lane1 reset signal active low */
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#define SERDES_C_GEN_RST_LN1_RST_N (1 << 7)
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/*
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* 0x0 – Normal / Active
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* 0x1 – Partial power down
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* 0x2 – Most blocks powered down (only LOS
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* active)
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* 0x3 – complete power down (IDDQ mode)
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* Can be asserted when Lane is in normal
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* mode. These modes provide an increased
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* power savings compared to reset mode.
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* Signal is overridden by por_n_i so has no
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* affect in power on reset state
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*/
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#define SERDES_C_GEN_RST_LN0_PD_MASK 0x00000300
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#define SERDES_C_GEN_RST_LN0_PD_SHIFT 8
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/*
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* 0x0 – Normal / Active
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* 0x1 – Partial power down
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* 0x2 – Most blocks powered down (only LOS
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* active)
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* 0x3 – complete power down (IDDQ mode)
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* Can be asserted when Lane is in normal
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* mode. These modes provide an increased
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* power savings compared to reset mode.
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* Signal is overridden by por_n_i so has no
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* affect in power on reset state
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*/
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#define SERDES_C_GEN_RST_LN1_PD_MASK 0x00000C00
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#define SERDES_C_GEN_RST_LN1_PD_SHIFT 10
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#define SERDES_C_GEN_RST_CPU_MEM_RESET (1 << 12)
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#define SERDES_C_GEN_RST_CPU_MEM_SHUTDOWN (1 << 13)
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#define SERDES_C_GEN_RST_CAPRI_APB_RESET (1 << 14)
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/**** status register ****/
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/*
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* 0x0 – No error
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* 0x1 – PHY has an internal error
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*/
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#define SERDES_C_GEN_STATUS_ERR_O (1 << 0)
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/*
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* 0x0 – PHY is not ready to respond to
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* cm0_rst_n_i and cm0_pd_i[1:0]. The
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* signals should not be changed.
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* 0x1 - PHY is ready to respond to
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* cm0_rst_n_i and cm0_pd_i[1:0]
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*/
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#define SERDES_C_GEN_STATUS_CM0_RST_PD_READY (1 << 1)
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/*
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* Indicates CMU PLL has locked to the
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* reference clock and all output clocks are at
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* the correct frequency
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*/
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#define SERDES_C_GEN_STATUS_CM0_OK_O (1 << 2)
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/*
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* 0x0 – PHY is not ready to respond to
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* ln0_rst_n and ln0_pd[1:0]. The signals
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* should not be changed.
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* 0x1 - PHY is ready to respond to lnX_rst_n_i
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* and lnX_pd_i[1:0]
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*/
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#define SERDES_C_GEN_STATUS_LN0_RST_PD_READY (1 << 3)
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/*
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* 0x0 – PHY is not ready to respond to
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* ln1_rst_n_i and ln1_pd[1:0]. The signals
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* should not be changed.
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* 0x1 - PHY is ready to respond to lnX_rst_n_i
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* and lnX_pd_i[1:0]
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*/
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#define SERDES_C_GEN_STATUS_LN1_RST_PD_READY (1 << 4)
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/*
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* Active low when the CPU performs a wait cycle (internally or externally
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* generated)
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*/
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#define SERDES_C_GEN_STATUS_CPU_WAITSTATE (1 << 5)
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#define SERDES_C_GEN_STATUS_TBUS_MASK 0x000FFF00
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#define SERDES_C_GEN_STATUS_TBUS_SHIFT 8
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/**** cfg register ****/
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/* 1- Swap 32 bit data on RX side */
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#define SERDES_C_LANE_CFG_RX_LANE_SWAP (1 << 0)
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/* 1- Swap 32 bit data on TX side */
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#define SERDES_C_LANE_CFG_TX_LANE_SWAP (1 << 1)
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/* 1 – invert rx data polarity */
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#define SERDES_C_LANE_CFG_LN_CTRL_RXPOLARITY (1 << 2)
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/* 1 – invert tx data polarity */
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#define SERDES_C_LANE_CFG_TX_LANE_POLARITY (1 << 3)
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/*
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* 0x0 –Data on lnX_txdata_o will not be
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* transmitted. Transmitter will be placed into
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* electrical idle.
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* 0x1 – Data on the active bits of
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* lnX_txdata_o will be transmitted
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*/
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#define SERDES_C_LANE_CFG_LN_CTRL_TX_EN (1 << 4)
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/*
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* Informs the PHY to bypass the output of the
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* analog LOS detector and instead rely upon
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* a protocol LOS mechanism in the SoC/ASIC
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* 0x0 – LOS operates as normal
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* 0x1 – Bypass analog LOS output and
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* instead rely upon protocol-level LOS
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* detection via input lnX_ctrl_los_eii_value
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*/
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#define SERDES_C_LANE_CFG_LN_CTRL_LOS_EII_EN (1 << 5)
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/*
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* If lnX_ctrl_los_eii_en_i = 1 then Informs
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* the PHY that the received signal was lost
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*/
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#define SERDES_C_LANE_CFG_LN_CTRL_LOS_EII_VALUE (1 << 6)
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/* One hot mux */
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#define SERDES_C_LANE_CFG_TX_DATA_SRC_SELECT_MASK 0x00000F00
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#define SERDES_C_LANE_CFG_TX_DATA_SRC_SELECT_SHIFT 8
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/* 0x0 - 20-bit 0x1 – 40-bit */
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#define SERDES_C_LANE_CFG_LN_CTRL_DATA_WIDTH (1 << 12)
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/**** stat register ****/
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/*
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* x0 – lane is not ready to send and receive data
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* 0x1 – lane is ready to send and receive data
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*/
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#define SERDES_C_LANE_STAT_LNX_STAT_OK (1 << 0)
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/*
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* 0x0 – received data run length has not
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* exceed the programmable run length
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* detector threshold
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* 0x1 – received data run length has
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* exceeded the programmable run length
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* detector threshold
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*/
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#define SERDES_C_LANE_STAT_LN_STAT_RUNLEN_ERR (1 << 1)
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/*
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* 0x0 – data on lnX_rxdata_o are invalid
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* 0x1 – data on the active bits of
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* lnX_rxdata_o are valid
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*/
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#define SERDES_C_LANE_STAT_LN_STAT_RXVALID (1 << 2)
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/*
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* Loss of Signal (LOS) indicator that includes
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* the combined functions of the digitally
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* assisted analog LOS, digital LOS, and
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* protocol LOS override features
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* 0x0 – Signal detected on lnX_rxp_i /
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* lnX_rxm_i pins
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* 0x1 – No signal detected on lnX_rxp_i /
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* lnX_rxm_i pins
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*/
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#define SERDES_C_LANE_STAT_LN_STAT_LOS (1 << 3)
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#define SERDES_C_LANE_STAT_LN_STAT_LOS_DEGLITCH (1 << 4)
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/**** reserved register ****/
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#define SERDES_C_LANE_RESERVED_DEF_0_MASK 0x0000FFFF
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#define SERDES_C_LANE_RESERVED_DEF_0_SHIFT 0
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#define SERDES_C_LANE_RESERVED_DEF_1_MASK 0xFFFF0000
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#define SERDES_C_LANE_RESERVED_DEF_1_SHIFT 16
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#ifdef __cplusplus
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}
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#endif
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#endif /* __AL_HAL_serdes_c_REGS_H__ */
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/** @} end of ... group */
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